Redundancy selector circuit for use in non-volatile memory...

Details Redundancy selector circuit for use in non-volatile memory... Redundancy selector circuit for use in non-volatile memory...

2008-01-01

2008-01-01

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189050, C365S189070

Reexamination Certificate

active

07315480

ABSTRACT:
A redundancy selector circuit for use in a non-volatile memory device include a ROM cell array, in which defective addresses are stored, including a plurality of ROM cells arranged in a matrix of rows and columns; a ROM controller for sequentially selecting rows of the ROM cell array at power-up; a sense amplifier block for sensing and amplifying data bits from ROM cells of the respective rows selected sequentially according to the control of the ROM controller; a latch block for receiving data bits sensed by the sense amplifier block through a switch circuit and latching the input data bits as a defective address; and a comparator block for detecting whether an address input in a normal operation matches one of the defective addresses stored in the latch block. As the rows are sequentially selected, the defective addresses of the ROM cell array are transferred to the latch block through the sense amplifier block by means of serial transfer.

REFERENCES:
patent: 5206831 (1993-04-01), Wakamatsu
patent: 6426910 (2002-07-01), Santin
patent: 6532181 (2003-03-01), Saito et al.
patent: 2002/0012282 (2002-01-01), Saito et al.
patent: 2004-515868 (2004-05-01), None
patent: 2004-246958 (2004-09-01), None
patent: 10-1999-0080912 (1999-11-01), None
patent: 10-20030024921 (2003-03-01), None

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