Redundancy fuse box and method for arranging the same

Details Redundancy fuse box and method for arranging the same Redundancy fuse box and method for arranging the same

1998-07-06

2000-05-23

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Having fuse element

365200, G11C 700

Patent

active

060672684

ABSTRACT:
A redundancy fuse box of a semiconductor memory device which minimizes address line loading by organizing fuse cells into fuse cell groups sharing the same sub-address line. The address signal therefore has to traverse across a shorter distance along the semiconductor device, which contributes to a reduction in cell line loading. The redundancy fuse box includes a plurality of fuse cells, each having a transistor and fuse, to which an address signal of a memory cell is applied. The respective fuse boxes are constructed as one fuse box by being laid out in the same place. The fuse box includes a plurality of fuse cells which receive the same address signal along a common sub-address line and is wired so that outputs of the fuse cells which received the same address signal contribute to different redundancy enable signals.

REFERENCES:
patent: 5327380 (1994-07-01), Kersh
patent: 5337277 (1994-08-01), Jang
patent: 5357470 (1994-10-01), Namekawa

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