Redundancy for a block-architecture memory

Details Redundancy for a block-architecture memory Redundancy for a block-architecture memory

1988-01-04

1989-02-21

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365200, 365230, G11C 700, G11C 1140

Patent

active

048071919

ABSTRACT:
A block architecture memory has two stacks of memory blocks. Between the two stacks are blocks of sense amplifiers. Each block of sense amplifiers is coupled to a memory block in each of the stacks of memory blocks via local data lines. Located at the bottom of each stack of memory blocks is a redundant block of columns of memory cells. There is a redundant sense amplifier located between and coupled to the redundant blocks of columns via local data lines. The redundant sense amplifier is also coupled to a redundant global data line. An input/output multiplexer is coupled to all of the global data lines. The multiplexer provides and receives external data. If one of the redundant columns is to replace a defective column for a particular address, then the redundant global data line carries data which corresponds to the external data.

REFERENCES:
patent: 4604730 (1986-08-01), Yoshida
patent: 4742486 (1988-05-01), Takemae et al.
patent: 4757474 (1988-07-01), Fukushi et al.

Affiliated with

Also associated with

Rating

Redundancy for a block-architecture memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Redundancy for a block-architecture memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy for a block-architecture memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1528136