Redundancy decoding circuit for a semiconductor memory device

Details Redundancy decoding circuit for a semiconductor memory device Redundancy decoding circuit for a semiconductor memory device

1997-10-30

1998-10-20

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 3652257, G11C 700

Patent

active

058256989

ABSTRACT:
A redundancy decoding circuit for a semiconductor memory device is shown which includes a comparator which decodes and outputs a redundant memory cell address in response to an address signal, where the comparator includes internal fuses that are coupled to an output terminal of the comparator and which can be selectively cut in order to determine the redundant memory cell address. The redundancy decoding circuit also includes a driving unit which supplies a driving current to the output terminal of the comparator in response to a switching control signal. A pulse generator generates a power up pulse having a predetermined width responsive to power up of the redundancy decoding circuit. A switching control signal generator, which includes a master fuse connected in series with a switching element, generates the switching control signal at a predetermined voltage level in response to the power up pulse generated by the pulse generator even when the master fuse is incompletely cut.

REFERENCES:
patent: 5574689 (1996-11-01), Morgan
patent: 5590085 (1996-12-01), Yuh et al.

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