Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-01-31
2001-08-14
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S189180, C365S189190
Reexamination Certificate
active
06275424
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a NAND flash memory device which is an example electrically erasable memory device, and more particularly, to a method and apparatus for reducing voltage stress across the gate oxide and across a junction of a high voltage transistor within a block of such an electrically erasable memory device.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, an example block
102
of a NAND flash memory device includes a first select gate
104
and a second select gate
106
and a plurality of word lines, as known to one of ordinary skill in the art of electronics. The example block
102
of the NAND flash memory device for example has a first word line
108
, a second word line
110
, and so on up to a sixteenth word line
112
. A typical NAND flash memory device has a plurality of such a block
102
. For example, a typical NAND flash memory device may have 1,024 instances of such a block
102
.
Each of the select gates or the word lines of the block
102
are coupled to the drain node of a respective high voltage transistor. The first select gate
104
is coupled to the drain node of a first high voltage transistor
114
, and the second select gate
106
is coupled to the drain node of a second high voltage transistor
116
. Similarly, the first word line
108
is coupled to the drain node of a third high voltage transistor
118
, the second word line
110
is coupled to the drain node of a fourth high voltage transistor
120
, and so on with the sixteenth word line
112
being coupled to a respective high voltage transistor
122
.
The gate node of each of the respective transistors coupled to the select gates or the word lines within the block
102
is coupled to a PASSVOLT node
124
. Each of the plurality of blocks of a NAND flash memory device has a separate respective PASSVOLT node.
The respective source node of each of the high voltage transistors within the block
102
is coupled to a respective vertical decode line of the NAND flash memory device, as known to one of ordinary skill in the art of electronics. The source node of the first high voltage transistor
114
is coupled to a first vertical decode line
115
, the source node of the second high voltage transistor
116
is coupled to a second vertical decode line
117
, the source node of the third high voltage transistor
118
is coupled to a third vertical decode line
119
, the source node of the fourth high voltage transistor
120
is coupled to a fourth vertical decode line
121
, and so on with the high voltage transistor
122
being coupled to a respective vertical decode line
123
. As known to one of ordinary skill in the art of electronics, each of the vertical decode lines are coupled to the source of each of a respective high voltage transistor from each of a plurality of blocks of the NAND flash memory device. During an erase operation of a block of the NAND flash memory device, all of the vertical decode lines
115
,
117
,
119
,
121
, and so on to
123
are coupled to ground.
Each of the select gates and the word lines within the block
102
of a NAND flash memory device is coupled to a plurality of core cells which may be a plurality of floating gate devices, as known to one of ordinary skill in the art of electronics. The control gate node of each of the plurality of core cells is coupled to a select gate or a word line within the block
102
.
Referring to
FIG. 2
, the cross-sectional view of an example high voltage transistor
202
within the block
102
is coupled to a respective plurality of core cells. Elements having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function. The example high voltage transistor
202
is within a semiconductor substrate
204
. The high voltage transistor
202
has a gate node
206
coupled to the PASSVOLT node
124
and has a source node
208
coupled to a ground node
126
during an erase operation of a block within the NAND flash memory device. A drain node
210
of the high voltage transistor
202
is coupled to the respective select gate line or the word line within the block
102
.
A core cell within the first well
212
of
FIG. 2
is a floating gate device, as known to one of ordinary skill in the art of electronics. The drain node
210
(and the respective select gate or word line) of the high voltage transistor
202
is coupled to each of the control gate node of a plurality of core cells disposed within a first well
212
. The drain node
210
of the high voltage transistor
202
of the block
102
may be coupled to each of the control gate node of approximately 4,000 core cells disposed within the first well
212
for example. In
FIG. 2
, just a first core cell
216
and a second core cell
218
are shown for clarity of illustration. Field oxide regions may isolate the core cells within the first well
212
. Just a first field oxide region
220
and a second field oxide region
222
within the first well
212
are shown in
FIG. 2
for clarity of illustration. The first well
212
is disposed within a second well
214
that separates the first well
212
from the semiconductor substrate
204
.
A first parasitic capacitor
224
is formed, between the first well
212
and the select gate or the word line. In addition, a second parasitic capacitor
226
is formed, between the drain node
210
forming the select gate or the word line and the semiconductor substrate
204
, from the PN junction formed by the drain node
210
and the semiconductor substrate
204
.
Referring to
FIG. 2
, the high voltage MOSFET
202
is an N-channel MOSFET, and the source node
208
and the drain node
210
are doped with an N-type dopant. The semiconductor substrate
204
is doped with a P-type dopant and is coupled to the ground node
126
. The first well
212
is doped with a P-type dopant, the second well
214
is doped with an N-type dopant, and the core cells within the first well
212
are N-channel floating gate devices.
As known to one of ordinary skill in the art of electronics, the core cells within the first well
212
of the block
102
are programmed by charge injection into the floating gate node of each of the core cells. In an erase operation, such charge is discharged from the floating gate node of each of the core cells. The erase operation is performed for a whole block of the NAND flash memory device. On the other hand, any charge injected into the floating gate nodes within other blocks, that are not being erased within the NAND flash memory device, are preserved.
Referring to
FIG. 3
, the voltage applied to the devices of a block of the NAND flash memory device during an erase operation of that block is shown. Elements having the same reference number in
FIGS. 1
,
2
, and
3
refer to elements having similar structure and function. For each high voltage transistor
202
within the block that is being erased, a turnon voltage of 2V is applied as the PASSVOLT to the gate node
206
of the high voltage transistor
202
. The high voltage transistor
202
turns on such that the drain node
210
is coupled to the ground node
126
at the source node
208
.
The select gate or the word line coupled to the drain node
210
is then also coupled to the ground node
126
. Thus, the control gate node of the floating gate devices within the first well
212
are coupled to the ground node
126
. A high voltage such as 20V for example is then applied to the first well
212
and the second well
214
. Such a bias at the control gate node of the core cells and at the first well
212
pulls out any charge that is stored within the floating gate node of the core cells during the erase operation of the block having the high voltage transistor
202
, as known to one of ordinary skill in the art of electronics.
Only a selected block of the NAND flash memory device has such biasing for an erase operation within such a selected block. The rest of the blocks of the NAND flash memory device are unselected blocks and are not erased. Any charge injected into the floating gate nodes of
Chen Pau-ling
Le Binh Quang
Advanced Micro Devices , Inc.
Choi Monica H.
Dinh Son T.
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