Reduction of standby current

Details Reduction of standby current Reduction of standby current

2002-06-13

2003-03-18

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S204000, C365S208000

Reexamination Certificate

active

06535443

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the reduction of standby power in a memory system that, e.g., includes dynamic random access memory (DRAM) or pseudo-static random access memory (pseudo SRAM). In particular, the present invention relates to reducing standby current by reducing the subthreshold leakage in the transistor in the memory cell by controlling the rate of discharge of the sense amplifier.
BACKGROUND
Electronic devices such as PDAs or wireless mobile or cellular phones, are driven by a battery power supply and use DRAM or pseudo-SRAM as data memory. One of the problems with a conventional DRAM or pseudo-SRAM schemes is data-retention. The data (voltage) stored in the memory cell decays with time, which requires that the memory cell be refreshed at predetermined intervals.
One source of data decay is subthreshold leakage current in the transistor in the memory cell.
FIG. 1
shows a typical unselected memory cell
10
including transistor
12
and capacitor
14
. In the worst case situation for data retention, memory cell
10
is connected to a bit line (BL)
16
, which is at a LOW potential, capacitor
14
is storing a HIGH data (voltage) and the word line (WL)
18
is LOW, i.e., transistor
12
is turned off. Thus, the source voltage, i.e., bit line
16
, is at the same LOW voltage as the gate voltage, i.e., word line
18
, which causes a subthreshold leakage current, shown as broken arrow
20
. The subthreshold leakage current causes the HIGH data in capacitor
14
to decay. Another source of data decay is the junction leakage current, shown as broken arrow
22
, caused by the source voltage being at the same LOW voltage as the substrate voltage.
The standby power consumption of DRAM or pseudo-SRAM devices is directly proportional the memory size and the frequency of the refresh operation. Thus, as the need for higher density DRAM or pseudo-SRAM increases in battery powered device, it is desirable to reduce the frequency of refresh to minimize standby power consumption. A proposed method of reducing the frequency of refresh is known as a boosted sense-ground scheme. The boosted sense ground scheme decreases the subthreshold leakage by boosting the LOW on bit line
16
to a boosted sense ground voltage (V
bsg
), thereby creating a negative gate-source voltage (V
gs
) and a negative source-substrate (V
bs
) voltage. Negative gate-source voltage (V
gs
) and negative source-substrate (V
bs
) exponentially decreases the subthreshold leakage current and the junction leakage current in transistor
12
. With the decrease in leakage current, the data-retention time of the memory cell is extended, which consequently permits a decrease in the frequency of refresh. Unfortunately, raising the source voltage to V
bsg
is difficult.
One known method of implementing the boosted sense ground scheme is shown as circuit
30
in
FIG. 2
, and is discussed in detail in Asakura et al., in IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, November. 1994, pages 1303-1307, which is incorporated herein by reference. As shown in
FIG. 2
, circuit
30
includes a differential amplifier
32
and a reference voltage generator
34
to raise the voltage on the bit line to the desired boosted sense ground voltage (V
bsg
).
FIG. 3
shows the simulated wave forms of both a conventional bit-line pair
36
and the boosted sense ground (
bsg
) pair
38
splitting as data is being read.
FIG. 3
shows that the bsg pair
38
senses the 1V bit line swing 1.2 ns faster than the conventional pair
36
. Unfortunately, while the use of a differential amplifier
32
and reference voltage generator
34
is effective, it is not efficient as it draws too much power. Thus, in a battery powered device, circuit
30
is undesirable due to the increase in power consumption caused by the reference voltage generator
34
and differential amplifier
32
.
Another known method of implementing the boosted sense ground scheme is shown as circuit
50
in FIG.
4
and is known as a precharged-capacitor-assisted sensing scheme, which is discussed in more detail in Kono, et a., in IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, August. 2000, pages 1179-1185, which is incorporated herein by reference. With the precharged-capacitor-assisted sensing scheme, a level controller
51
and decoupling capacitors
52
and
54
are used to discharge the bit lines
53
and
55
until the data level of the bit lines is at the desired voltage V
bsg
.
FIG. 5
shows the simulated wave forms of both a conventional
bsg
scheme pair
58
and the precharged-capacitor-assisted sensing scheme pair
60
splitting as data is being read. The use of decoupling capacitors
52
and
54
and level controller
51
requires power for each charge and discharge and is, therefore, undesirable for battery powered devices.
Accordingly, what is needed is a memory circuit that produce a boosted sense ground potential to reduce subthreshold leakage to minimize standby current, without requiring additional power consumption to achieve the boosted sense ground potential.
SUMMARY
A memory circuit, in accordance with the present invention, includes a sense amplifier that generates a boosted sense ground potential by controlling the rate of discharge of the sense amplifier towards ground without holding the sense amplifier at a constant voltage level. Thus, the memory circuit does not require a boosted sense ground voltage regulator or precharged capacitors, but nevertheless, minimizes the subthreshold leakage found in unselected memory cells. Consequently, the frequency of refresh can be decreased to reduce standby current.
The memory circuit includes a plurality of bit lines, word lines and memory cells disposed between the bit lines and word lines. The memory circuit also includes a sense amplifier for reading data from a selected memory cell. The sense amplifier is electrically coupled to ground potential through at least two transistors, a large transistor and a small transistor. A control circuit is used to control when the large transistor and small transistor are turned on and off. The control circuit turns the large transistor on to discharge the sense amplifier toward ground quickly, which ensures a fast sense speed for the sense amplifier. In one embodiment, both the large and small transistors are turned on to quickly discharge the sense amplifier toward ground potential. The large transistor is turned off after a short period so that the sense amplifier is coupled to ground only through the small transistor. The small transistor continues to discharge the sense amplifier toward ground but at a much slower rate than the large transistor. The small transistor is turned off prior to the sense amplifier reaching ground potential. Consequently, the sense amplifier provides a decreasing boosted sense ground potential to the bit line without the use of a boosted sense ground voltage generator.
Another aspect of the present invention is a method of controlling a memory circuit that includes a sense amplifier including discharging the sense amplifier towards ground at a first rate, and discharging the sense amplifier towards ground at a second rate that is slower than the first rate, and terminating the discharge of the sense amplifier towards ground prior to the sense amplifier reaching ground. The different discharge rates ensures that the sense amplifier will achieve a fast sense speed, as well as hold a boosted sense ground potential without the use of a voltage regulator or precharged capacitors.


REFERENCES:
patent: 4751681 (1988-06-01), Hashimoto
patent: 5297092 (1994-03-01), Johnson
patent: 5973957 (1999-10-01), Tedrow
patent: 5982690 (1999-11-01), Austin
patent: 6204698 (2000-02-01), Zhang

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