Reduction of silicon oxynitride film delamination in integrated

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

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257642, 257637, 257759, 257760, 257774, 257758, H01L 5100

Patent

active

06133619&

ABSTRACT:
Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.

REFERENCES:
patent: 5470802 (1995-11-01), Gnade et al.
patent: 5661344 (1997-08-01), Havemann et al.
patent: 5747880 (1998-05-01), Havemann et al.
patent: 5818111 (1998-10-01), Jeng et al.

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