Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-08-29
2010-06-01
Everhart, Caridad M (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000, C438S799000, C438S678000, C257SE21586, C257SE21579, C257SE21584
Reexamination Certificate
active
07727885
ABSTRACT:
A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.
REFERENCES:
patent: 5698071 (1997-12-01), Kawamoto
patent: 6455939 (2002-09-01), Raina et al.
patent: 7045455 (2006-05-01), Zhang et al.
patent: 2003/0017696 (2003-01-01), Yen
patent: 2004/0161930 (2004-08-01), Ma et al.
patent: 2004/0214430 (2004-10-01), Ruelke et al.
patent: 2005/0023693 (2005-02-01), Fitzsimmons et al.
patent: 2005/0032354 (2005-02-01), Chu et al.
patent: 2005/0042889 (2005-02-01), Lee et al.
patent: 2005/0067297 (2005-03-01), Tench et al.
patent: 2005/0106370 (2005-05-01), Takai et al.
patent: 2005/0245071 (2005-11-01), Wu et al.
patent: 2006/0040487 (2006-02-01), Inoue et al.
patent: 2006/0084260 (2006-04-01), Boyers et al.
patent: 2006/0118962 (2006-06-01), Huang et al.
patent: 2006/0170106 (2006-08-01), Tseng et al.
patent: 2006/0172525 (2006-08-01), Werner et al.
Chatterjee Basab
Chevacharoenkul Sopa
Lin Ching-Te
Matz Phillip Daniel
Newton Kenneth Joseph
Brady III Wade J.
Everhart Caridad M
Franz Warren L.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Reduction of punch-thru defects in damascene processing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduction of punch-thru defects in damascene processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduction of punch-thru defects in damascene processing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4241505