Reduction of plasma damage for HDP-CVD PSG process

Details Reduction of plasma damage for HDP-CVD PSG process Reduction of plasma damage for HDP-CVD PSG process

2000-01-11

2002-07-23

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S017000, C438S624000, C438S631000, C438S695000, C438S778000

Reexamination Certificate

active

06423653

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is a method for depositing a a phospho-silicate glass (PSG) inter-layer dielectric (ILD) gapfill on topographic substrate layers employed within microelectronics fabrications of 0.15 micron and beyond device generations. Specifically, this method employs a high density plasma chemical- vapor deposition (HDP-CVD) process, modified so as to produce a significantly reduced degree of plasma damage and a concurrently smaller likelihood of device shifts and failures.
2. Description of the Related Art
Semiconductor integrated circuit microelectronics fabrications are formed from layered semiconductor substrates upon whose surfaces metallic lines are deposited in complex topographic patterns. In the newest generation of such fabrications, the heights and widths of these lines and the spacings between them can be 0.15 microns and less. The deposition of various types of dielectric materials over these substrate layers and metallic patterns is required both to isolate them from subsequent overlays of new substrates and patterns and to produce the necessary device structures from the patterns themselves. In the earlier generation of devices, in which lines and spacings were of the order of 0.5 microns to 0.6 microns, the interlayer dielectric deposition of dielectrics such as boron- phosphorus doped silicate glass (BPSG) were carried out using sub-atmospheric chemical vapor deposition (SA-CVD) methods. While these techniques were adequate for those device sizes, the 0.15 &mgr;m and smaller dimensions characterizing the most recent generation of devices require newer processes such as HDP-CVD. Not only does the plasma enhanced deposition provide a better gapfill for the smaller spacings, due to its combined sputtering and plasma-enhanced deposition nature, but the deposited layer is denser than that produced by SA-CVD and requires no additional annealing steps in the process. A state of the art plasma deposition device having a plasma processing chamber configured with top and side antenna coils for RF tuning and coupling to the plasma is described by Redeker et al, U.S. Pat. No. 5,800,621. C. Y. Chang and S. M. Sze (“ULSI Technology,” McGraw-Hill Co's, Pub., New York, 1996, page 423) remark of HDP-CVD deposition that: “Because of the ideal properties of ILD and gap filling, the HDP oxide will become the dominating ILD process for devices 0.35 &mgr;m and below.” It has been demonstrated that ILD layers deposited by HDP-CVD can be effectively planarized for the subsequent microcircuit fabrication (see Yao et al. in U.S. Pat. No.
5,814,564)
. It has also been demonstrated that HDP-CVD gap-fill layers deposited in a stack conformation can lead to enhanced planarity and throughput (see Jain, U.S. Pat. No. 5,621,241).
Notwithstanding the demonstrable positive attributes of HDP-CVD, the method raises the problem of damage to the metal lines during deposition with corresponding subsequent shifts in device properties and even complete device failures. Plasma deposition damage results primarily from the impact energies of the ionized reactant species being deposited on the substrate and metal lines. These energies, in turn, are extremely difficult to control, as they are a result of two factors: the RF fields ionizing and heating the plasma and the bias potential of the substrate relative to the ionized species.
It is recognized that there is a need to find a mechanism to substantially reduce the effects of plasma damage in HDP-CVD. One such method, involving the growth of an intermediate protective layer between the metallized substrate and the HDP deposited ILD, is described by Wang et al. (U.S. Pat. No. 5,679,606.) The present invention is a method for reducing the damage caused by HDP-CVD by a novel variation in the schedule of energies supplied to the wafer (substrate) and plasma during the actual deposition process.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a method for producing high density plasma chemical vapor deposition (HDP-CVD) of inter-layer dielectrics (ILD) while substantially reducing the concurrent degree of device damage encountered in the present state of the art.
A second object of this invention is to provide such a method that operates solely within the context of the actual deposition and does not require intermediate processes such as the prior deposition of buffering or insulating layers.
In accord with the objects of the present invention, there is provided is a method for producing gap filling inter-layer dielectric depositions upon a topographic substrate by high density plasma chemical vapor deposition (HDP-CVD) applied in such a manner as to produce said deposition with a resulting significant reduction of plasma deposition induced damage.
In accord with the objects of the present invention there is provided a new schedule of RF power inputs transferring power to the plasma within the chamber of a plasma deposition device in a series of steps that results in said deposition which significantly reduces the damage to the substrate produced by the energetic deposition species that impact said substrate. This new schedule, which differs from that utilized in the current state of the art for HDP-CVD, is shown to significantly reduce the HDP-CVD damage resulting from ion impacts to the substrate.
In accord with the objects of the present invention there is provided a method for producing dielectric depositions upon a substrate having a silicon oxide layer by high density plasma chemical vapor deposition (HDP-CVD) applied in such a manner as to produce said deposition with a resulting significant reduction of plasma deposition induced damage.
In accord with the objects of the present invention there is provided a method for determining the amount of plasma damage produced by a high density plasma chemical vapor deposition (HDP-CVD) and evaluating the efficacy of the particular method of producing said deposition, using a measurement of a flatband voltage as an indicator of the amount of damage.
The method of the present invention may be employed where the microelectronics fabrication is a semiconductor integrated circuit microelectronics fabrication and the topographic substrate consists of a configuration of metal lines and spaces requiring an inter-layer dielectric gapfill produced by HDP-CVD utilizing state of the art plasma deposition apparatus.


REFERENCES:
patent: 5621241 (1997-04-01), Jain
patent: 5679606 (1997-10-01), Wang et al.
patent: 5800621 (1998-09-01), Redeker et al.
patent: 5814564 (1998-09-01), Yao et al.
patent: 5913140 (1999-06-01), Roche et al.
patent: 6114182 (2000-09-01), Tabara
C.Y. Chang et al., “ULSI Technology”, The McGraw-Hill Companies, Inc., New York, NY, 1996, p. 423.

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