Reduction of n-channel parasitic transistor leakage by using low

Details Reduction of n-channel parasitic transistor leakage by using low Reduction of n-channel parasitic transistor leakage by using low

1997-04-26

2000-07-11

Nelms, David

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438681, 438784, 438787, H01L 2131

Patent

active

060872756

ABSTRACT:
A method of manufacturing a semiconductor device with increasing threshold voltage for parasitic transistor by forming a low power-low pressure phosphosilicate glass layer on the active regions and the field oxide regions.

REFERENCES:
patent: 4546016 (1985-10-01), Kern
patent: 4952254 (1990-08-01), Lee et al.
patent: 5409743 (1995-04-01), Bouffard et al.

Affiliated with

Also associated with

Rating

Reduction of n-channel parasitic transistor leakage by using low does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduction of n-channel parasitic transistor leakage by using low, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduction of n-channel parasitic transistor leakage by using low will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-542073