Reducing PECL voltage variation

Details Reducing PECL voltage variation Reducing PECL voltage variation

2001-10-16

2003-04-29

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S073000, C326S074000, C326S027000

Reexamination Certificate

active

06556041

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates generally to circuit design. More particularly, this invention relates to a method for reducing PECL voltage variation.
2. Background Art
In electronic circuits, the system power supply can be shown as an equivalent circuit
10
as shown in FIG.
1
. Specifically, the equivalent circuit
10
includes: a system power supply source
12
; a system resistance (Rs)
14
; a system inductance (Ls)
16
; and a chip capacitance (Rc)
18
. Each of these system components
12
,
14
,
16
, and
18
represent an equivalent value of all of the combined respective components in the power supply system. The performance of the circuit
10
is frequency dependent. As shown in the graph of
FIG. 2
, as the frequency of the system increases, the resistance of the circuit increases as well. This increase in resistance continues until a peak
20
is reached at a resonance frequency. Finally, the resistance will subside at even higher frequencies.
The rate of increase in the resistance of the circuit as the frequency approaches its resonance value is quantified as a “Q” value. The “Q” value is calculated as Q=((L/C))/R; where L is the system inductance value; where C is the system capacitance value; and where R is the system resistance value. As shown in
FIG. 2
, under normal operations, the equivalent circuit
10
has a very high Q value
24
near the resonance frequency. A high current transient with the high Q region of the frequency band causes significant noise in the power supply system. Supply noise can result in such problems as voltage variation, signal jitter, signal stability, component or logic malfunction, signal interference, etc. For instance, a PLL circuit will have more jitter in the presence of power supply noise, which effectively leads to a reduction in the speed at which a chip can operate. Voltage variation is a significant problem because the indeterministic distribution of power to system components can lead to a loss of system performance.
It would be advantageous to decrease the Q value of the power supply system and thereby reduce voltage variation. A reduced Q value
26
is also shown in FIG.
2
. This Q value
26
would have the advantage of substantially reducing the voltage variation of the respective system.
FIG. 3
shows a prior art method of reducing the Q value for a positive emitter coupled logic (“PECL”) power supply system. PECL involves standard emitter coupled logic devices running off a positive power supply. Thus, components powered by PECL usually operate of partial swing signals as opposed to full swing signals. Typically, PECL is used for a receiver circuit
32
that inputs a partial swing system clock and outputs a full swing system clock to a phase locked loop (“PLL”) (not shown). However, although PECL is fast, the use of PECL for the receiver circuit to the PLL introduces jitter on the clock signal from the receiver circuit to the PLL.
The receiver circuit
32
is just one of many types of components that are commonly included in an integrated circuit. Each of these components often has a dedicated power supply that is unique and separate from the power supplies of other components. The prior art method used in
FIG. 3
involves inserting a de-coupling capacitor
34
across the power supply in parallel with the receiver
32
. However, the capacitor
34
takes up a significant amount of space on the chip. With chip space at a premium, a space efficient method of reducing voltage variation for a circuit using PECL voltage is needed.
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for reducing voltage variation in a PECL based component comprises supplying power to the PECL based component and connecting a resistance in parallel with the PECL based component.
According to another aspect, a method for reducing voltage variation in a PECL based component comprises a step of supplying power to the PECL based component and a step of shunting a resistance in parallel with the PECL based component.
According to another aspect, an apparatus for reducing voltage variation in PECL based component comprises means for supplying power to the PECL based component and means for connecting an impedance in parallel with the PECL based component.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5633602 (1997-05-01), Sanwo et al.
patent: 5874837 (1999-02-01), Manohar et al.

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