Reducing extrinsic base resistance in an NPN transistor

Details Reducing extrinsic base resistance in an NPN transistor Reducing extrinsic base resistance in an NPN transistor

2005-05-17

2005-05-17

Smoot, Stephen W. (Department: 2813)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C438S343000, C438S373000, C438S528000

Reexamination Certificate

active

06893931

ABSTRACT:
A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a cap layer situated over the base layer. According to this embodiment, the method for fabricating the NPN bipolar transistor further comprises fabricating an emitter over the base layer, where the emitter defines an intrinsic and an extrinsic base region of the base layer. The emitter may comprise, for example, polycrystalline silicon. The method for fabricating the NPN bipolar transistor further comprises implanting germanium in the extrinsic base region of the base layer so as to make the extrinsic base region substantially amorphous. The method for fabricating the NPN bipolar transistor further comprises implanting boron in the extrinsic base region of the base layer.

REFERENCES:
patent: 5159424 (1992-10-01), Morishita
patent: 5407838 (1995-04-01), Ohnishi et al.
patent: 5512772 (1996-04-01), Maeda et al.
patent: 6620665 (2003-09-01), Sugahara et al.

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