Reducing DQ pin capacitance in a memory device

Details Reducing DQ pin capacitance in a memory device Reducing DQ pin capacitance in a memory device

2008-01-15

2008-01-15

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C327S112000, C365S185020, C365S191000

Reexamination Certificate

active

07319621

ABSTRACT:
A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a method according to the present disclosure allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired. The logic circuits disclosed to accomplish the reduction in DQ pin capacitance not only conserve the existing chip real estate, but also do not negatively affect the speed with which signals may be output from the electronic device.

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