Reducing digit equilibrate current during self-refresh mode

Details Reducing digit equilibrate current during self-refresh mode Reducing digit equilibrate current during self-refresh mode

2005-09-20

2005-09-20

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189110, C365S230060, C365S236000

Reexamination Certificate

active

06947346

ABSTRACT:
Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refreshed. An auto-refresh counter and row address block are used to generate a section address and a row address of memory cells to refresh. Each sub-array has a given row of memory cells refreshed before another row of memory cells in a given sub-array is refreshed.

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