Reduced power redundancy address decoder and comparison circuit

Details Reduced power redundancy address decoder and comparison circuit Reduced power redundancy address decoder and comparison circuit

2006-12-05

2006-12-05

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189070, C365S225700

Reexamination Certificate

active

07145817

ABSTRACT:
A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.

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