Reduced power consumption sram

Details Reduced power consumption sram Reduced power consumption sram

1996-06-25

1998-03-17

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365207, 365208, 36523003, 365156, G11C 700, G11C 702, G11C 800, G11C 1100

Patent

active

057294984

ABSTRACT:
The continuing need for faster and denser SRAM memories places a constant increased demand on the power consumption of the memory devices. Much of the power consumption occurs during the pre-charge phase where it is common practice to bring up all pre-charge circuits at once and hold them active until the memory operations are complete. This invention describes a design where each pre-charge circuit connected to a group of memory cells through bit lines is activated at a separate time from the other pre-charge circuits. Thus each pre-charge circuit is active only during the time that useful work is being done with that portion of the memory. This reduces power consumption by not powering on circuits and precharging bit lines before they are actually needed.

REFERENCES:
patent: 5367488 (1994-11-01), An
patent: 5383158 (1995-01-01), Ikegami
patent: 5412606 (1995-05-01), Lee
patent: 5432747 (1995-07-01), Fuller et al.
patent: 5506811 (1996-04-01), McLaury
patent: 5528522 (1996-06-01), Kamisaki
patent: 5563832 (1996-10-01), Kagami

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