Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-06-27
2002-05-14
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000, C257S723000
Reexamination Certificate
active
06388333
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to a semiconductor device suitable for forming a three-dimensional structure in which a plurality of semiconductor devices are provided in a stacked state.
In association with reduction in size, weight and thickness of electronic apparatuses, reduction in size and thickness is required for semiconductor devices used in the electronic apparatuses. In order to satisfy such a requirement, a semiconductor package has been changed from a quadra-flat package to a ball grid array (BGA) package or chip size package (CSP).
A fan-out type package is popular among those packages. In the fan-out type package, a semiconductor chip is mounted on a redistribution substrate (generally referred to as an interposer) and external connection terminals are arranged around the semiconductor chip.
2. Description of the Related Art
FIG. 1
is a cross-sectional view of a conventional fan-out type semiconductor device. In
FIG. 1
, a semiconductor chip
3
is mounted on an interposer
1
that is formed of a polyimide substrate or a glass-epoxy substrate. The semiconductor chip
3
is encapsulated by a seal resin
2
. The semiconductor chip
3
is fixed to the interposer
1
by a die-bonding material
6
in a face-up state in which a circuit forming surface of the semiconductor chip
3
faces upward. Bonding pads
5
and ball pads
8
are formed on the upper surface of the interposer
1
, and the bonding pads
5
are connected to the respective ball pads
8
by wiring patterns.
Electrodes of the semiconductor chip
3
are connected to the respective bonding pads
5
by gold (Au) wires
4
. The surface of the semiconductor chip
3
on which the semiconductor chip
3
is-mounted is encapsulated by the seal resin
2
such as epoxy resin so as to protect the semiconductor chip
3
, the Au wires
4
, the bonding pads
5
and the ball pads
8
. Additionally, VIA holes
9
are formed in the interposer
1
at positions corresponding to the ball pads
8
so that the ball pads
5
are exposed in the VIA holes
9
. Solder balls
7
are provided on the bonding pads
5
serving as bottoms of the VIA holes
9
opening on the lower surface of the interposer
1
. Accordingly, the semiconductor chip
3
is electrically connected to the solder balls
7
serving as external connection terminals via the interposer
1
. The solder balls
7
protrude from the lower surface of the interposer
1
.
FIG. 2
is a cross-sectional view of a CSP type semiconductor device in which a semiconductor chip is mounted by a flip-chip mounting method. In
FIG. 2
, parts that are the same as the parts shown in
FIG. 1
are given the same reference numerals, and descriptions thereof will be omitted.
In
FIG. 2
, the semiconductor chip
3
is mounted on the interposer
1
by a flip-chip mounting method in a face-down state in which the circuit forming surface of the semiconductor chip
3
faces the interposer
1
. That is, the semiconductor chip
3
has a connection bumps
12
, which are connected to the bonding pads
5
. An under fill material
11
is filled between the semiconductor chip
3
and the interposer
1
so that the semiconductor chip
3
is fixed to the interposer
1
by the under fill material
11
. Similar to the semiconductor device shown in
FIG. 1
, through holes (VIA holes)
9
are provided in the interposer
1
, and the solder balls
7
protrude from the lower surface of the interposer
1
.
In the above-mentioned semiconductor devices, the mounting area of the package including the semiconductor chip is reduced so that the package size is reduced to almost the size of the semiconductor chip. Accordingly, the reduction in the two-dimensional size of the package is considered to be almost the limit. Thus, the reduction in size of the semiconductor devices must be directed to the three-dimensional scheme. That is, in order to reduce the size of the semiconductor devices, consideration must be given on not only how to reduce a mounting area but also how to reduce a mounting volume.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful semiconductor device in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a semiconductor device which can directly connect to another semiconductor device in a stacked arrangement so that a plurality of the semiconductor devices can be mounted on a mounting board in a three-dimensional structure by stacking one on another.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a semiconductor device comprising: a first semiconductor element; a redistribution substrate having a first surface and a second surface opposite to the first surface, the first semiconductor element being mounted on the first surface; a plurality of electrode pads arranged on the first surface of the redistribution substrate, the electrode pads being electrically connected to the first semiconductor element; a plurality of protruding electrodes provided on the respective electrode pads; and a plurality of through holes extending from the second surface of the redistribution substrate to the respective electrode pads, wherein the first semiconductor element is encapsulated by a seal material, and a height of each of the protruding electrodes from the first surface is larger than a height of a sealed portion of the first semiconductor element from the second surface.
According to the above-mentioned invention, the through holes are formed in the redistribution substrate such as an interposer so that the back side of the electrode pads are exposed on the bottom of the respective through holes. Additionally, each of the protruding electrodes is higher than the sealed portion of the first semiconductor element, when two semiconductor devices are stacked one on another, the sealed portion of the upper semiconductor device can be accommodated in a space between the redistribution substrates of the upper and lower semiconductor devices while the protruding electrodes of the upper semiconductor device are bonded to the electrode pads of the lower semiconductor device through the through holes of the redistribution substrate of the lower semiconductor device. That is, the distance between the upper semiconductor device and the lower semiconductor device can be defined only by the protruding electrodes of the upper semiconductor device being bonded to the electrode pads of the lower semiconductor device. Thus, the stacked structure of the semiconductor devices can be achieved in a simple structure. Additionally, the electrode pads can be freely positioned around the first semiconductor element on the first surface of the redistribution substrate by forming wiring patterns on the first surface under the first semiconductor element.
Additionally, there is provided according to another aspect of the present invention a semiconductor device comprising: a first semiconductor element; a redistribution substrate having a first surface and a second surface opposite to the first surface, the first semiconductor element being mounted on the first surface; a plurality of electrode pads arranged on the first surface of the redistribution substrate, the electrode pads being electrically connected to the first semiconductor element; a plurality of through holes extending from the second surface of the redistribution substrate to the respective electrode pads; and a plurality of protruding electrodes formed on the respective electrode pads through the respective through holes, wherein the first semiconductor element is encapsulated by a seal material, and a height of each of the protruding electrodes from the second surface is larger than a height of a sealed portion of the first semiconductor element from the electrode pads.
According to the above-mentioned invention, the through holes are formed in the redistribution substrate such
Ando Fumihiko
Onodera Hiroshi
Orikawa Kouhei
Takashima Akira
Taniguchi Fumihiko
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Potter Roy
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