Reduced bus turnaround time in a multiprocessor architecture

Details Reduced bus turnaround time in a multiprocessor architecture Reduced bus turnaround time in a multiprocessor architecture

2008-06-10

2008-06-10

Trujillo, James K (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C710S112000, C710S113000, C710S119000, C710S305000, C714S747000

Reexamination Certificate

active

07386750

ABSTRACT:
Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus handoff. The method may also include bypassing data from recovery latches and instead receiving data from pipeline latches into core logic, the received data mirroring data driven onto the system bus.

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