Recovering bit lines in a memory array after stopped clock...

Details Recovering bit lines in a memory array after stopped clock... Recovering bit lines in a memory array after stopped clock...

2007-05-15

2007-05-15

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S149000, C365S233100, C365S229000, C712S039000, C712S043000, C712S229000

Reexamination Certificate

active

11173119

ABSTRACT:
In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the first and second bit line precharge circuits. The first and second bit line precharge circuits are each configured to precharge the first bit line and the second bit line. The control circuit is coupled to receive an indication that one or more clocks are being restarted after a period of stopped clock operation, and is configured to activate both the first and second bit line precharge circuits responsive to the indication and independent of an operation to the memory that was interrupted by the period of stopped clock operation, if any.

REFERENCES:
patent: 5434822 (1995-07-01), Deleganes et al.
patent: 5642324 (1997-06-01), Ghosh et al.
patent: 6041401 (2000-03-01), Ramsey et al.
patent: 6084454 (2000-07-01), Holst
patent: 7046573 (2006-05-01), Takazawa et al.
patent: 7082069 (2006-07-01), Chou et al.
patent: 7126867 (2006-10-01), Kang et al.

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