Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
2005-10-06
2010-06-22
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S226000, C712S015000
Reexamination Certificate
active
07743236
ABSTRACT:
The present invention provides a reconfigurable processing apparatus enabling clusters to utilize a shared functional unit by using data and a validity signal received from the clusters by way of a network therebetween. In the reconfigurable processing apparatus comprising one or more clusters which are reconfigured based on configuration information, the shared functional unit accepts an input data and an input valid signal from the clusters, the input valid signal starts up the shared functional unit so as to operate the input data received with the input valid signal and output, to the cluster, an output data as the operation result and an output valid signal for notifying of the cluster as an output destination of the aforementioned output data.
REFERENCES:
patent: 4509116 (1985-04-01), Lackey et al.
patent: 5594918 (1997-01-01), Knowles et al.
patent: 5838165 (1998-11-01), Chatter
patent: 5842031 (1998-11-01), Barker et al.
patent: 6487651 (2002-11-01), Jackson et al.
patent: 6665795 (2003-12-01), Roth et al.
patent: 6745318 (2004-06-01), Mansingh et al.
patent: 6954845 (2005-10-01), Arnold et al.
patent: 7039737 (2006-05-01), Dorr et al.
patent: 7126381 (2006-10-01), Schmit et al.
patent: 7191321 (2007-03-01), Bernstein et al.
patent: 2001/0049816 (2001-12-01), Rupp
patent: 2002/0029330 (2002-03-01), Kamano et al.
patent: 2004/0001445 (2004-01-01), Stansfield
patent: 2004/0088527 (2004-05-01), Huppenthal et al.
patent: 2004/0103264 (2004-05-01), Fujii et al.
patent: 2004/0125103 (2004-07-01), Kaufman et al.
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 2006/0184766 (2006-08-01), Pires Dos Reis Moreira
patent: 2007/0058805 (2007-03-01), Ohkuma et al.
patent: 2008/0024506 (2008-01-01), Lindholm et al.
patent: 0 325 384 (1989-01-01), None
patent: 0 576 749 (1994-01-01), None
patent: 54-061851 (1979-05-01), None
patent: 59-16072 (1984-01-01), None
patent: 63-291155 (1988-11-01), None
patent: 02-005173 (1990-01-01), None
patent: 06-348492 (1994-12-01), None
patent: 2000-201066 (2000-07-01), None
patent: 2001-312481 (2001-11-01), None
patent: 2002-073331 (2002-03-01), None
patent: 2004-133781 (2004-04-01), None
patent: 2004511042 (2004-04-01), None
patent: WO 03/036507 (2003-05-01), None
patent: WO 2004/023290 (2004-03-01), None
patent: 2004/042560 (2004-05-01), None
Michael Taylor “The Raw Prototype Design Document”; Published: Sep. 6, 2004; Pertinent pp. 1-50.
Michael Taylor “The Raw Prototype Design Document”, MIT, Nov. 1999, pp. 1-89.
H. Ito et al; Dynamically Reconfigurable Logic LSI-PCA-1; 2001;Symposium on VLSI Circuits Digest of Technical Papers; Jun. 14-16, 2001; pp. 103-106: XP010551509; ISBN: 4-89114-014-3; pp. 103-105; figures 1-3, 5.
Xingcha Fan et al; Architecture Design Of A Fully Asynchronous VLSI Chip For DSP Custom Applications;Proceedings of the International Symposium on Circuits and Systems; San Diego, May 10-13, 1992;Proceedings of the Intemaitonal Symposium on Circuits and Systems; (ISCAS); New York; IEEE; US; vol. 4 Conf. 25; May 3, 1992; pp. 2112-2115; XP010061680; ISBN: 0-7803-0593-0; pp. 2113; left-hand column; figure 1.
Naohisa Takahashi et al; A Data Flow Processor Array System; Design and Analysis;Proceeding of the Annual Symposium on Computer Architecture; Stockholm, 1983; Proceedings of the Annual International Symposium on Computer Architecture; Los Angeles; IEEE Comp. Soc. Press, US; vol. SYMP. 10; Jun. 13, 1983; pp. 243-250; XP007900128; ISBN: 0-8186-8159-4.
Scott Hauck et al; The Chimaera Reconfigurable Functional Unit; Field-Programmable Custom Computing Machines; 1997; Proceedings;The 5thAnnual IEE Symposium OnNapa Valley; CA: USA;IEEE Comput. Soc; US; Apr. 16, 1997; pp. 87-96; XP010247471; ISBN: 0-8186-8159-4.
Gerard J.M. Smit et al; Lessons Learned From Designing The Montium A Coarse-Grained Reconfigurable Processing Tile; System-On-Chip; 2004; Proceedings.2004 International Symposium onTampere; Finland; Nov. 16-18, 2004; Piscataway; NJ; USA; IEEE; Nov. 16, 2004; pp. 29-32; XP010779386; ISBN: 0-7803-8558-6; p. 30; left-hand column, paragraph 3; figure 1.
John Teifel et al; An Asynchronous Dataflow FPGA Architecture;IEEE Transactions on Computers; vol. 53; No. 11; Nov. 2004; pp. 1376-1392; XP002379722; ISSN: 0018-9340.
English Translation of European Official Communication dated Dec. 18, 2007.
Japanese Office Action dated Mar. 24, 2009, 5 pages.
Koichiro Furuta et al. (NEC Corporation); “A Dynamically Reconfigurable Logic LSI with Flexible Reconfiguration Control Mechanism”; Technical Report of IEICE; ED99-55; SMD99-29; ICD99-37; pp. 1˜8, The Institute of Electronics, Information and Communication Engineers.
Fujisawa Hisanori
Saito Miyoshi
Alrobaye Idriss N
Arent & Fox LLP
Chan Eddie P
Fujitsu Limited
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