Recessed, sidewall-sealed and sandwiched poly-buffered LOCOS...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation

Reexamination Certificate

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Details

C438S447000, C438S448000, C438S702000

Reexamination Certificate

active

06297130

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor isolation methods and regions and, more particularly, to LOCOS isolation methods and regions.
BACKGROUND OF THE INVENTION
Advanced VLSI-class semiconductor devices are being designed with sub-micron moat-to-moat spacing. Working (or active) semiconductor devices are fabricated on the moat region on the semiconductor wafer. These devices must be adequately isolated from one another to prevent adverse interaction (e.g., leakage current or shorting) between these devices. A well known technique for forming isolation regions between the moat regions is the LOCOS field oxidation technique, which has become an industry mainstay. Conventional LOCOS techniques, however, have been inadequate or marginal at best when used with sub-micron VLSI products. In particular, “moat encroachment” (also known as “bird's beaking”) is a major problem. It is caused be lateral oxidation into the moat regions during field oxide growth. This encroachment at moat edges and corners results in a drastic decrease of moat dimensions and is severely detrimental for maintaining sub-micron moat-to-moat geometries.
Several isolation techniques have been developed in recent years for use with VLSI CMOS and BiCMOS products. For instance, the Poly-Buffered LOCOS (PBL) Isolation technique is currently used with VLSI designs having 1.2 micron minimum moat-to-moat spacing. Poly-buffered LOCOS is a modification to the industry standard LOCOS isolation process. The modification includes the step of adding a thin buffer layer of polysilicon (poly) between the underlying pad oxide and the overlying moat nitride film. The polysilicon layer allows the use of a thick moat nitride film during the field oxidation process by relieving stresses in the silicon lattice normally present during LOCOS oxidation.
SUMMARY OF THE INVENTION
In accordance with the teaching of the present invention, the disclosed recessed, sidewall-sealed and sandwiched poly buffered LOCOS process reduces or eliminates the disadvantages and shortcomings associated with relevant prior art methods for forming localized isolation regions for VLSI technology. In one embodiment, using photolithography, plasma etch, and channel stop implant steps, the present invention comprises the steps of forming a pad layer of silicon dioxide on a semiconductor body or substrate; a first silicon nitride layer is thereafter formed on the silicon dioxide layer; a polysilicon layer is thereafter formed on the first silicon nitride layer; a second silicon nitride layer is thereafter formed on the polysilicon layer next to the isolation regions. A nitride sidewall seal is formed thereafter around the perimeter of the semiconductor moat regions, followed by the creation of a silicon recess. LOCOS field oxidation techniques are used to grow the isolation oxide. If nitride sidewall seals are used, a preferred embodiment places a pad oxide buffer layer between the nitride sidewall and the semiconductor body. While the elimination of the sidewalls is feasible, it is not preferred.
In an attempt to fabricate field oxide isolation regions with little or no encroachment (bird's beaking) into the moat, an additional fabrication step can be added to the above. In this embodiment a shallow trench is etched into the semiconductor substrate in the inverse moat region after formation of the nitride side-wall.


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