Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-07-25
2010-11-16
Lindsay, Jr., Walter L (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S281000, C438S306000, C438S589000, C438S591000, C438S703000, C257SE23147, C257SE21428
Reexamination Certificate
active
07833860
ABSTRACT:
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.
REFERENCES:
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5163180 (1992-11-01), Eltoukhy et al.
patent: 5208177 (1993-05-01), Lee
patent: 5429970 (1995-07-01), Hong
patent: 5550400 (1996-08-01), Takagi et al.
patent: 5567634 (1996-10-01), Hebert et al.
patent: 5661071 (1997-08-01), Chor
patent: 5693547 (1997-12-01), Gardner et al.
patent: 5937281 (1999-08-01), Wu
patent: 6069398 (2000-05-01), Kadosh et al.
patent: 6130469 (2000-10-01), Bracchitta et al.
patent: 6346846 (2002-02-01), Bertin et al.
patent: 6355955 (2002-03-01), Gardner et al.
patent: 6388305 (2002-05-01), Bertin et al.
patent: 6498071 (2002-12-01), Hijzen et al.
patent: 6509624 (2003-01-01), Radens et al.
patent: 6611165 (2003-08-01), Derner et al.
patent: 6700176 (2004-03-01), Ito et al.
patent: 6713839 (2004-03-01), Madurawe
patent: 6724238 (2004-04-01), Derner et al.
patent: 6740957 (2004-05-01), Porter
patent: 6897543 (2005-05-01), Huang et al.
patent: 7033867 (2006-04-01), Porter
patent: 7084456 (2006-08-01), Williams et al.
patent: 7211482 (2007-05-01), Kim et al.
patent: 7238573 (2007-07-01), Park
patent: 2002/0115257 (2002-08-01), Inagawa et al.
patent: 2003/0232285 (2003-12-01), Hao et al.
patent: 2005/0040462 (2005-02-01), Koh
Kim et al., 3-Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse, Journal of Semiconductor Technology and Science, vol. 3, No. 4, Dec. 2003, pp. 205-210.
Office Action of U.S. Appl. No. 10/933,161 dated Sep. 8, 2006.
Office Action of U.S. Appl. No. 10/933,161 dated Feb. 26, 2007.
Office Action of U.S. Appl. No. 10/933,161 dated Apr. 23, 2007.
Office Action of U.S. Appl. No. 10/933,161 dated Oct. 19, 2007.
Office Action of U.S. Appl. No. 10/933,161 dated Mar. 6, 2008.
Office Action of U.S. Appl. No. 10/933,161 dated Aug. 5, 2008.
Pre-Brief Appeal Conference Decision of U.S. Appl. No. 10/933,161 dated May 12, 2009.
Office Action of U.S. Appl. No. 10/933,161 dated May 19, 2009.
McCollum, et al., “Reliability of Antifuse-Based Field Programmable Gate Arrays for Military and Aerospace Applications”, Actel Corporation, Sunnyvale, CA, USA, pp. 1-6, Sep. 2001.
Lindsay, Jr. Walter L
Micro)n Technology, Inc.
Pompey Ron
Wells St. John P.S.
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