Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-06
2001-05-01
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S183000, C438S199000, C438S291000, C438S300000, C438S595000
Reexamination Certificate
active
06225173
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with ultra-shallow source/drain extensions.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects, which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the drain and source extensions, as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
As transistors disposed on integrated circuits (ICs) become smaller, transistors with shallow and ultra-shallow source and drain extensions have become more difficult to manufacture. For example, smaller transistors should have ultra-shallow source and drain extensions (less than 30 nanometer (nm) junction depth). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation and diffusion doping techniques make transistors on the IC susceptible to short-channeling effects, which result in a dopant profile tail distribution that extends deep into the substrate. Also, conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extensions vertically into the bulk semiconductor substrate.
Thus, there is a need for a method of manufacturing ultra-shallow source and drain extensions that does not utilize a conventional double implant process. Further still, there is a need for transistors that have ultra-shallow junction source and drain extensions. Even further still, there is a need for an efficient method of manufacturing source and drain extensions.
SUMMARY OF THE INVENTION
The present invention relates to a method of manufacturing an integrated circuit. The method includes providing a plurality of gate structures between a source region and a drain region in a semiconductor substrate, each of the gate structures includes a dummy material. The method also includes removing the dummy material, thereby leaving a cavity, etching a recess in the substrate within the cavity and partially in the source region and in the drain region. The recess forms an ultra-shallow source extension and an ultra-shallow drain extension. The method also includes providing a doped semiconductor material, in the cavity.
The present invention further relates to a method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors. Each transistor has a source, a drain, and a gate structure disposed between the source and the drain. The gate structure includes a first gate material disposed over a gate oxide. The method includes steps of depositing an insulative material over the top surface of the semiconductor substrate and over the gate structures, removing a portion of the insulative material to expose the first gate material, removing the first gate material from the gate structures, removing the gate oxide, etching the substrate underneath the gate oxide, providing a thin gate oxide, and providing a second gate material in the gate structure.
The method even further relates to a damascene gate process of forming shallow source and drain extensions. The process includes steps of providing a plurality of transistors that include a source region, a drain region, and at least a portion of a gate structure on a top surface of a silicon substrate. The gate structure includes a gate connector located between the source region and the drain region. The process further includes steps of removing the gate conductor from the gate structure, thereby leaving a cavity in the gate structure, and etching within the cavity to provide a recessed portion in the top surface of the substrate, thereby forming the shallow source and drain extensions.
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Advanced Micro Devices , Inc.
Foley & Lardner
Hack Jonathan
Niebling John F.
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