Recess Pt structure for high k stacked capacitor in DRAM and...

Details Recess Pt structure for high k stacked capacitor in DRAM and... Recess Pt structure for high k stacked capacitor in DRAM and...

2001-10-18

2003-07-22

Niebling, John F. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S396000, C257S303000, C257S306000, C257S310000

Reexamination Certificate

active

06596580

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to integrated circuit (IC) memory devices and, more particularly, to the fabrication of stacked capacitor structures in Dynamic Random Access Memories (DRAMs) and similar devices.
A platinum (Pt) electrode has been used in high k stacked capacitor structures in Dynamic Random Access Memory (DRAM) and Flash Random Access Memory (FRAM) devices because of its high work function. Stacked capacitors are connected to the devices through polycrystalline silicon (polysilicon) plugs (or, more simply, “polyplugs”). A barrier layer is required between bottom Pt electrode and the polyplug to avoid reaction between Pt and polysilicon and the oxidation of the polyplug during the deposition of high k capacitor films. However, after the bottom electrode is patterned by Reactive Ion Etch (RIE), the interface of Pt electrode and barrier layer is exposed, and diffusion of oxygen through the interface has been observed. The interface layer due to oxygen diffusion increases the contact resistance and decreases the capacitance, and therefore should be avoided.
It is therefore an object of the present invention to provide a capacitor structure and method of making the same which avoids the interface layer due to oxygen diffusion.
According to the invention, there is provided a recessed Pt electrode deposited in situ with the barrier layer. Since the barrier layer and Pt electrode are deposited in situ and the most exposed area during Chemical-Mechanical Polish (CMP) is Pt, the formation of an oxide layer on the barrier layer surface during CMP is avoided. There is more space for dielectric film (than a sidewall spacer structure) since the barrier layer is recessed and no spacer is required. The oxygen diffusion path is longer due to the lateral recess of the barrier. The process provides more tolerance to misalignment.


REFERENCES:
patent: 5381302 (1995-01-01), Sandhu et al.
patent: 6407422 (2002-06-01), Asano et al.
patent: 6454860 (2002-09-01), Metzner et al.
patent: 6455424 (2002-09-01), McTeer et al.
patent: 2002/0084481 (2002-07-01), Lian et al.

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