Receiver circuit with constant input impedance

Details Receiver circuit with constant input impedance Receiver circuit with constant input impedance

1996-07-25

1998-10-13

Nelms, David C.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 30, H03K 1716

Patent

active

058217681

ABSTRACT:
For interference-free transmission of high-frequency signals, the receiver must be terminated with the characteristic impedance of the transmission line. This can be achieved by a single base-connection circuit, but in this case the input impedance is dependent on the current flow and is therefore not exactly constant. Adding a second base-connection circuit makes the circuit symmetrical, so that opposite effects are canceled, which makes the input impedance constant. Production in both bipolar technology and in MOS technology is possible.

REFERENCES:
patent: 3573489 (1971-04-01), Sramek
patent: 5363332 (1994-11-01), Murabayashi
patent: 5412262 (1995-05-01), Nishio et al.
Kawamura, T. et al.: An Extremely Low-power Bipolar Current-mode I/O Circuit for Multi-Gbit's Interfaces. In: 1994 Symposium on VLSI Circuits Digest of Technical Papers, S. 31,32.
Murabayashi, F. et al., 3.3-V BiCMOS Circuit Techniques for A 120-mHz Microprocessor. In: IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994 S. 298-302.

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