Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Patent
1998-05-27
2000-12-05
Yoo, Do Hyun
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
711123, 711201, 711206, 711220, G06F 1200
Patent
active
061579815
ABSTRACT:
A memory and memory architecture for use by a processor executing real time code and a system on a chip including the processor and memory containing the code. An effective address is maintained in a cache directory. In the preferred embodiment memory, individual functions are loaded into physical memory at permanently selected locations and selected by the effective address in the cache directory. By preselecting task storage locations, system performance may be tuned or optimized to assure predictable performance or task execution.
REFERENCES:
patent: 3979726 (1976-09-01), Lange et al.
patent: 4654782 (1987-03-01), Bannai et al.
patent: 4885680 (1989-12-01), Anthony et al.
patent: 5132927 (1992-07-01), Lenoski et al.
patent: 5179681 (1993-01-01), Jensen
patent: 5210841 (1993-05-01), Johnson
patent: 5274834 (1993-12-01), Kardach et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5564030 (1996-10-01), Whitted, III et al.
patent: 5568442 (1996-10-01), Kowalczyk et al.
patent: 5586293 (1996-12-01), Baron et al.
patent: 5623621 (1997-04-01), Garde
patent: 5636224 (1997-06-01), Voith et al.
patent: 5640533 (1997-06-01), Hays et al.
patent: 5652872 (1997-07-01), Richter et al.
patent: 5940873 (1999-08-01), Mou
patent: 5968145 (1999-10-01), Maeda et al.
Mitsubishi Microcomputers M3Z000D4AFP, Single-Chip 32-bit CMOS microcomputer, Mitsubishi Electric, entirety, Aug. 1997.
Jim Handy, "The Cache Memory Book", Academic Press, pp 48-50 and 60-62, 1993.
Intel, Microprocessors, vol. I, Intel Corp, pp 2-36 thru 2-41, 1992.
M. Morris Mano, "Computer System Architecture", Prentice-Hall, Inc, p. 122, 1976.
Blaner Bartholomew
Burkhart Henry Harvey
Herzl Robert Dov
Lauricella Kenneth Anthony
Ogilvie Clarence Rosser
International Business Machines - Corporation
Kim Hong
Walsh, Esq. Robert A.
Yoo Do Hyun
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