Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-11-15
2005-11-15
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C703S027000, C716S030000, C716S030000
Reexamination Certificate
active
06965972
ABSTRACT:
A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache directories, each connected to one of the arrays, and a plurality of global coherence directories, each connected to one of the arrays. Each of the global coherence directories maintain information on all memory lines remotely cached by each of the cache directories.
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Furuta et al, Feb. 15-17, 1999, ISSCC, pp. 364-479.
Nanda Ashwini
Sugavanam Krishnan
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
Nelson, Esq. Eustus D.
Peugh Brian R.
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