Real time DRAM eliminating a performance penalty for crossing a

Details Real time DRAM eliminating a performance penalty for crossing a Real time DRAM eliminating a performance penalty for crossing a

1998-02-05

1999-12-28

Robertson, David L.

Static information storage and retrieval

Read/write circuit

Multiplexing

36523002, 711 5, G11C 800

Patent

active

060090197

ABSTRACT:
A memory system allows page boundaries to be crossed in successive reads of a Dynamic Random Access Memory (DRAM) without the necessity of waiting for another page of memory to be read out of a memory array of the DRAM. The memory is divided into multiple banks, each of which has a Bit-Line Sense Amplifier (BLSA) capable of holding one page of memory. Successive pages of memory are stored in separate banks, and may be activated or deactivated while data from another page is being read. The memory system is operable whether the successive reads are sequential or out-of-order.

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