Static information storage and retrieval – Read/write circuit – Multiplexing
Patent
1988-02-16
1990-02-20
Shaw, Gareth D.
Static information storage and retrieval
Read/write circuit
Multiplexing
3642392, 3642436, 364243, 364238, 3642387, 364942, 364964, 365239, 365240, 341100, 341101, 370 77, 370 78, 370 79, 370 80, G06F 1200
Patent
active
049032402
ABSTRACT:
A multiphase memory array is read out using two multiplexers and a demultiplexer under the control of a state machine. The state machine enables one portion of the memory array at a time using a gate to multiplex the memory portion outputs. While a particular portion is enabled, a bit multiplexer associated with that portion is directed by the controlling state machine to sequentially select each bit at the current address in that memory portion for output. A shift register demultiplexer performs serial to parallel conversion on the sequential bits from each memory portion to convert them to a readback byte or word for output. After the byte or word has been read out, the state machine enables the next portion of the memory array and repeats the multiplexing and demultiplexing process for the data at the same address in that memory portion. When all of the memory portions have read out, the address to the memory array is changed and the whole process is repeated for the data at the new address.
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Griffith Boulden G.
Ray Gopal C.
Shaw Gareth D.
Tektronix Inc.
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