Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-11-28
2001-10-23
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S210130, C365S185210
Reexamination Certificate
active
06307797
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic circuits, and, more particularly, to reading devices for integrated circuit memories. The present invention may be applied especially, but not exclusively, to erasable programmable read only memories (EPROMs) or one-time-programmable (OTP) type non-volatile electrically programmable memories.
BACKGROUND OF THE INVENTION
The cells of a memory are usually organized in matrix form with bit lines and word lines. The bit lines are the conductors through which the state stored in a cell is read. Thus, when a memory cell is addressed in read mode, the corresponding word line is selected and the corresponding bit line is connected to a read device.
In general, it is not just one but several memory cells that are read when a memory word is read. The cells forming a memory word typically belong to the same word line, and a respective bit line corresponds to each cell. In read mode, each one of these bit lines is connected to a corresponding reading device, where all of the reading devices may be identical.
Since the bit lines include a large number of cells, they provide capacitance because of the sum of the individual capacitances of the components themselves, namely the cells and selection transistors, and because of the topology of the bit lines. They also provide resistance because of the materials used, the contact resistances, the metallization, and the internal resistances of the transistors of the cells.
For these reasons, the reading device usually includes a precharging circuit to charge the equivalent capacitor of a bit line selected in read mode to a determined precharging read voltage. Then, a current generator sets up a current in the bit line. If the selected cell absorbs current, a voltage variation will be detected on the line. In the case of EPROM type memory cells, the reading device furthermore includes a voltage limiter to limit the voltage of the bit lines to a level close to one volt. This is to eliminate the risk of memory cells being programmed during the read access operations.
In addition, the reading is often based on a comparison between the current that flows in the cell selected in read mode and the current that flows in a reference cell. For example, in the case of an EPROM or OTP memory, the two possible states of a cell of the memory are the blank state (which is also the state of being erased by UV rays) and the programmed state. The reference cells are all in the same known state, which is generally the blank state. In this state, the floating-gate transistor of the memory cell has a low threshold voltage of about 1.4 volts, for example. In the programmed state, this threshold voltage becomes higher (e.g., 5.5 volts).
The principle of a reading relying on a comparison is based on the fact that if the cell selected in read mode is in the erased state, it can absorb as much current as the reference cell placed in the same conditions of bias. If this cell is provided with only a fraction of this current, it will make the bit line voltage collapse, and this fact will be detected.
Thus, in practice, a read current generator injects a given read current Iref into the reference bit line associated with the reference cell. It also injects a fraction of this reference current (e.g., half or one-third) into the data bit line associated with the cell to be read. A read differential amplifier receives a signal coming from the data bit line at the first differential input and a signal coming from the reference bit line at the second differential input.
If the cell that is read is erased, it draws more current than the fraction of reference current given to it by the current generator. The first differential input is then drawn to a voltage U lower than the voltage Uref at the second input of the differential amplifier. The output of the amplifier switches over in one direction. If, on the other hand, the cell that is read is programmed, it absorbs very low current or no current at all. The first differential input is then drawn to a voltage U higher than the voltage Uref at the second input of the differential amplifier and the output of the amplifier switches over to the other direction.
Thus, a common reading device includes a precharging circuit for each of the bit lines that limits the bit line voltage, a read current generator connected to the bit lines, and a read amplifier that provides the information at the output. The precharging circuit is in practice a current/voltage converter that fulfils three different functions. The first function is supplying current to precharge the bit lines. The second function is limiting the bit line potential to a specified precharging read voltage to eliminate involuntary programming. Furthermore, the third function is supplying a signal to the amplifier, with a voltage that varies strongly with the current on the associated bit line, in the evaluation stage.
The reading device therefore goes through several stages of operation. These include starting up the precharging circuits, activation of the read current generators, selection and precharging of the bit lines, and selection of the word line (row decoding). The voltage levels seen by the read amplifier are then often close to Vdd and are related not to the state of the selected cell but to the precharging circuit.
At this time, the cell selected in read mode either absorbs or does not absorb current. If current is absorbed (in the case of a blank or erased cell), this current is first given by the bit line capacitance and then by the associated read current generator. This absorption of current produces a great variation of voltage in the signal applied at the input to the differential amplifier, causing it to switch over. Even so, the output of the amplifier oscillates throughout the time of the variations on the bit lines. This slows down the setting up of the real data at the output.
In practice, the sequencing operations needed to start up the various circuits of the reading device and the parasitic oscillations of the amplifier lengthen the read access time. One and one-half clock cycles are needed to obtain the output data element. By way of example, a typical read access time may be 80 nanoseconds, and a maximum read access time may be 130 nanoseconds.
To avoid oscillations at the output of the amplifier, reading devices may use a latch instead of the read differential amplifier. Yet, it is then necessary to provide an additional external sequencing. This is to provide the activation signal for this latch as a function of all the time constraints and as a function of the sensitivity of the latch. This activation signal often comes from a control unit using reference circuits known as “dummy” circuits in the art. These circuits are sized to obtain sufficient latitude, allowing for the worst cases of propagation. In the prior art, the reading is slowed down because of the successive sequencing operations needed and the oscillation of the amplifier.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the read access time of memories, namely the time in which the data reflecting the state stored in one or more memory cells becomes available at an output. In one example, a maximum read access time of 25 nanoseconds may be provided instead of the typical prior art time of 80 nanoseconds.
Another object of the invention is to provide a fast-access reading device for a memory using a differential amplifier.
A reading device according to the present invention includes, in addition to a circuit for precharging data bit lines and reference bit lines to a precharging voltage level close to one volt, a circuit for precharging inputs of an amplifier to an intermediate precharging voltage level between the precharging voltage level (e.g., on the order of one volt) and the level of the supply voltage Vdd. In practice, this value is about 1.5 volts and balances the inputs of the differential amplifier. As such, in the next evaluation phase, the output of the amplifier switche
Fournel Richard
Varisco Laura
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Nguyen Tan T.
STMicroelectronics S.A.
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