Read zero DRAM

Details Read zero DRAM Read zero DRAM

2000-06-09

2001-05-29

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S205000, C365S208000

Reexamination Certificate

active

06240008

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a dynamic random access memory (DRAM), particularly to a DRAM having data access path optimized for reading a ‘zero.’
BACKGROUND OF THE INVENTION
Among the critical issues for a conventional DRAM, ratio of bit line capacitance to cell capacitance, if not well controlled, deleteriously affects the initial charge sharing time to generate the required differential signal for proper sensing. Also, in a conventional DRAM, a data bit ‘one’ requires longer time to restore, thereby undesirably lengthening the write cycle time. Additionally, cell leakage affecting the stored ‘one,’ which can hurt production ramp-up. Furthermore, even though DRAM is better than static random access memory (SRAM) in terms of available density and structural simplicity, SRAM is still better than DRAM in term of data access speed.
Thus, a need exists for an improved DRAM that offers the size advantage of DRAM without sacrificing the speed. That is, a need exists for an improved DRAM that decreases the gap between its speed and SRAM's speed. Additionally, a need exists for an improved DRAM that does not have bad ratio of BL capacitance to cell capacitance. Furthermore, a need exists for an improved DRAM that is not difficult to control the initial charge sharing time to generate the required differential for proper sensing. Further still, a need exists for an improved DRAM that does not have problem with cell leakage that affects the stored ‘one’ and hurts production ramp-up.
SUMMARY
The invention is drawn to a method and apparatus for improving random access cycle time and pause capability in dynamic random access memory (DRAM). Specifically, the invention provides an improved DRAM that offers the size advantage of DRAM without sacrificing the speed. That is, the invention provides an improved DRAM that decreases the gap between its speed and the speed of static random access memory (SRAM). Additionally, the invention provides an improved DRAM that does not have bad ratio of BL capacitance to cell capacitance. Furthermore, the invention provides an improved DRAM that is not difficult to control the initial charge sharing time to generate the required differential for proper sensing. Further still, the invention provides an improved DRAM that does not have problem with cell leakage to affect the stored ‘one’ and production ramp-up.
Preferably, a DRAM with a conventional cell layout has its data access path adapted to access a ‘zero’ faster than a ‘one.’ The DRAM comprising two capacitors coupled respectively to two neighboring word lines. The two capacitors are also coupled respectively to two neighboring bit lines (BL's) via two pass gates. Specifically, the two capacitors are utilized together to represent data as complementary data bits on the two capacitors. In so doing, a ‘zero’ is ensured to be stored in either one of the two capacitors. In turn, a voltage level ‘zero’ is ensured to be maintained on the BL coupled to the capacitor storing the ‘zero’ data bit.
As parts of the DRAM's data access path, each of a sense amplifier (SA) and a write driver amplifies a ‘zero’ and a ‘one’ unequally by amplifying the ‘zero’ faster than the ‘one.’ The SA and the write driver take advantage of the fact that a voltage level ‘zero’ is ensured to be maintained in either one of the two BL's.
The DRAM does not need to operate in the differential sensing mode. Rather, the DRAM can operate in either the differential sensing mode or the conventional mode. The switch between the differential and the conventional sensing modes can be implemented without having to alter the conventional cell layout of the DRAM.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.


REFERENCES:
patent: 5682343 (1997-10-01), Tomishima et al.
patent: 5742544 (1998-04-01), Foss
patent: 5781483 (1998-07-01), Shore

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