Read/write speed up circuit for integrated data memories

Details Read/write speed up circuit for integrated data memories Read/write speed up circuit for integrated data memories

1976-11-08

1978-01-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

340173FF, 365154, 365204, 365233, G11C 1140, G11C 700

Patent

active

040706567

ABSTRACT:
An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.

REFERENCES:
patent: 3736572 (1972-05-01), Tu

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