Read/write amplifier having vertical transistors for a DRAM...

Details Read/write amplifier having vertical transistors for a DRAM... Read/write amplifier having vertical transistors for a DRAM...

2001-06-01

2004-11-23

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S063000, C365S203000, C365S206000

Reexamination Certificate

active

06822916

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to read/write amplifiers for DRAM memories which are embodied with vertical transistors.
Dynamic Random Access Memories (DRAM memories) represent the most important type of memories for storing digital information. Each DRAM memory cell comprises a transistor for addressing the cell and a capacitance for storing a charge which represents the information stored in the memory cell.
The memory cells are connected in matrix-type arrangements. What is called a word line and a bit line lead to each memory cell, all the memory cells of a row being connected to the same word line or to two word lines which are respectively connected to every second cell and each of the rows of the matrix of memory cells being connected to one or two bit lines. Activation of a specific word line enables all the memory cells connected thereto to be read via their bit lines, written to or refreshed with regard to their information content. Refreshing is necessary in DRAM memory cells since the charge stored in the capacitance is lost over the course of time on account of leakage currents, especially in the case of integrated modules.
In order to read out the information contained in memory cells, or in order to refresh the information, what are called read/write circuits are used, which are respectively connected usually to two bit lines. The coupling to two bit lines enables a comparison of the charge differences and thus simplifies the assessment of a memory cell content.
FIG. 1
shows an example of such a read/write device—known in the prior art—for reading DRAM memory cells. This circuit essentially comprises a multiplexer section A, an evaluation section B and a precharge/equalize section C. The heart of the circuit is formed by the evaluation section B with a flip-flop which comprises two transistor pairs having transistors of the same polarity, namely the nMOS transistors T
1
and T
2
, and respectively the pMOS transistors T
4
and T
5
. In the present example, the read/write amplifier is connected to two bit lines, the bit line BL and the reference bit line BBL. In this case, BBL is connected via the connection
10
to the gate of the transistor T
1
, while BL is connected via the connection
12
to the gate of the transistor T
2
. Furthermore, BBL is connected via the connection
11
to one of the source/drain regions of the transistor T
2
and BL is connected via the connection
13
to a source/drain region of the transistor T
1
.
The other source/drain region of the two transistors is connected via the SAN connection
14
to the transistor T
3
, which can be switched via the connection
15
by means of the signal NSET via the signal line, or interconnect
17
, in order to be able to be pulled to ground (GND). This is done via the ground line
18
and the connection
16
, which is connected to the other source/drain region of the transistor T
3
. The second transistor pair, comprising the transistors T
4
and T
5
, is connected up in the same way to the bit lines BL and BBL, but VDD rather than ground can be applied to the transistor T
6
. This circuit arrangement effects a segregation of the possible signal states to form unambiguous signal levels, which allows assessment of the cell content with regard to logic 1 or logic 0.
The multiplexer section A comprises the two transistors T
7
for the bit line BL and T
8
for the bit line BBL. In this case, the bit line BL is connected via the connection
34
to a source/drain region of the transistor T
7
, while the bit line BBL is connected via the connection
31
to the transistor T
8
. Via the MUX line
36
, a multiplexer signal can be fed to the connections
33
and
30
of the transistors T
7
and T
8
, with the result that the latter switch on. In the event of switch-on, the voltage present on BL, and respectively BBL, is forwarded via the connections
35
and
32
.
Finally, the precharge/equalizer section C comprises the three transistors T
9
, T
10
and T
11
. While BBL is connected via a connection
40
to a source/drain region of the transistor T
10
, BL is connected via the connection
42
to a source/drain region of the transistor T
9
. The respective other source/drain regions of the two transistors T
9
and T
10
are connected via the connection
44
to the VBLEQ signal line
46
. The transistor T
11
is simultaneously connected to both bit lines in its source/drain region via the connection
41
to BBL and via the connection
43
to BL. All three gate regions of the transistors T
9
, T
10
and T
11
are connected via the connection
45
to the EQ line
47
. The circuit described here for a read/write circuit is to be regarded as by way of example. It is not intended to restrict the invention and can undergo numerous variations.
DRAM memory modules are subject to intense cost pressure. Today's DRAM memories are realized practically exclusively as integrated semiconductors in which the arrangements of memory cells, word line including word line driving arrangement, bit line including the bit line driving arrangement, etc, are projected on an integrated circuit directly as structures of a silicon wafer. The main factor in the costs of fabricating integrated circuits is the size of the silicon surface used in each case. Therefore, under the existing cost pressure, there are great efforts to make the chip area for a specific number of memory cells, including their support logic, as small as possible. Continual miniaturization is practically permanently necessary for reasons of cost pressure. To that end, the inherent architecture of the DRAM memory cell is also permanently being optimized. Starting from the 1 Gbit generation, the architecture of such a DRAM memory cell enables an area consumption of less than 8 F
2
, where F represents the minimum feature size that can be produced lithographically or half a grid width of a bit line in a sequence of parallel bit lines. A consequence of this reduction of area is that for the bit line architecture there is a transition from a “folded” concept, in which typically two word lines which respectively address every second cell are routed beside one another, to what is called the “open” concept, in which just one word line is used, which can address each cell of a row. A comparison of the quantities of charge of two adjacent bit lines is at present impossible in this way. Therefore, a parallel reference bit line cannot be used as a reference. Instead, a reference bit line is routed to another cell array in order still to be able to carry out a comparison of the voltages of an addressed bit line and of a nonaddressed reference bit line. The omission of the second, parallel bit line reduces the available width for the read/write amplifier. As a consequence of DRAM memory cell miniaturization, with a conventional word-line and bit-line arrangement, the available space for the read/write amplifier decreases in width from hitherto 8 F to 4 F. In a further embodiment, two bit lines which lead to different cell arrays, for example cell arrays adjacent in strips, are arranged one above the other.
Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide a read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. Instead, it has been necessary to adapt the arrangement of the read/write circuits on the chip to the conditions of the reduced cell size. However, such arrangements once again increase the area requirement of the read/write circuits to be accommodated and thus adversely affect the overall costs of each individual DRAM memory module.
SUMMARY OF THE INVENTION
The invention is thus based on the object of providing a read/write circuit which can be inserted into the reduced grid with a width of just 4 F of modern DRAM memory modules.
This object is achieved by providing an integrated read/write circuit that includes at least one vertical transistor and

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