Read-preferred SRAM cell design

Details Read-preferred SRAM cell design Read-preferred SRAM cell design

2006-10-17

2008-10-14

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189190, C365S189110, C365S202000, C365S205000, C365S207000, C365S190000, C365S189090

Reexamination Certificate

active

07436696

ABSTRACT:
A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an α ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a β ratio of between about 1.45 and 5.

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patent: 2005/0265070 (2005-12-01), Liaw
Seevinck, E., et al., “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Oct. 1987, pp. 748-754, vol. SC-22, No. 5, IEEE.
Ichikawa, T., et al., “A New Analytical Model of SRAM Cell Stability in Low-Voltage Operation,” IEEE Transactions on Electron Devices, Jan. 1996, pp. 54-61, vol. 43, No. 1, IEEE.

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