Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-09-18
2003-04-01
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S154000
Reexamination Certificate
active
06542423
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to the design of register arrays and a system that implements the design.
BACKGROUND OF THE INVENTION
FIG. 1
is block diagram of a conventional register array system
100
comprising m read enable ports
110
(where m is a positive number), m NAND gates
120
, m input inverters
130
, n output inverter
150
(where n is another positive number), and an array of m×n data registers DATA {
0
,
0
}, . . . DATA{
0
, n−1}, . . . , DATA {m−1,0}, . . . , and DATA {m−1, n−1}, each DATA register for storing a data value. The register array
100
further comprises m read word lines, wln[
0
], wln[
1
], . . . , and wln[n], and n read bit lines, bl[
0
], bl[
1
], . . . , and bl[n], interconnecting the m×n data registers. Each read word line is coupled to an output of one of the m NAND gates
120
through one of the m input inverters
150
. Each NAND gate receives as its inputs a clock signal CLK and an input signal from one of the m input ports
110
. The read bit lines are read through the output inverters
130
.
In the register array
100
, each data register, such as DATA {i,j}, where i=0, 1, . . . , m and j=0, 1, . . . , n, is coupled to a corresponding pair of read word line wln[i] and read bit line bl[j] by a stack of two N-type field-effect transistors (NFET) N
1
and N
2
. The gate voltage of the NFET N
1
is regulated by the corresponding read word line, while the gate voltage of the NFET N
2
is regulated by the data value stored in the data register. The first diffusion region of the transistor N
1
is coupled to the corresponding bit line, while the drain of the transistor N
1
is coupled to the first diffusion region of the transistor N
2
, which drain is coupled to a low voltage V
SS
, or the ground.
FIG. 2A
is a plot of the CLK signal and
FIG. 2B
is a truth table for the conventional register array
100
. When the clock signal CLK is low, the read bit lines are precharged through a precharging circuit (not shown in FIG.
1
). During a pre-charge phase, the read bit lines bl[
0
], . . . , and bl[n] are charged to a voltage V
DD
. In the conventional register array system
100
, each read bit line bl[j], where j=0, 1, . . . , n, has an associated capacitance, C
1
. This capacitance includes the diffusion capacitance of NFET N
1
, from 0 to m−1 rows and the wire capacitance of the read bit line which connects to all of the NFETs and to the output inventors, and also includes the input gate capacitance of the output mxerta. There is thus a quantity of charge, Q=C
1
V
DD
, associated with precharging the read bit line.
When the CLK is high, the register array is read or evaluated. During a normal functional mode of operation, a read-enable signal REN[i], where i=0, 1, . . . , m, is raised and supplied to an input port
110
to select the data registers along one of the m read word lines. A NAND gate
120
and input inverter
130
pair receives the read enable signal and the CLK signal to turn on the transistors N
1
on the read word line. With transistors N
1
on the read word line being turned on, each read bit line is directly coupled to the first diffusion region of the corresponding NFET N
2
on the read word line. The read bit line will remain charged at V
DD
or discharge to V
SS
, depending on whether the corresponding NFET N
2
is turned on by the data value in the corresponding data register. Therefore, the output of the read bit line, which is read through an inverter
150
, reflects the stored data of the corresponding data register.
During the normal functional mode of operation, only one of the read enable signals REN[i] is raised such that content associated with only one read word line is selected. However, as shown in
FIG. 1
, during a scan test mode, a scan input Si, typically comprising a random pattern, is input into the input ports
110
and a scan output So is read. The scan out So is connected to scan input ports of a succeeding block of circuitry. With a random pattern scan input Si in the scan test mode, more than one read word lines may be selected, i.e., multiple data registers along a bit line may be read, leading to a multiple-hot condition, as explained in more detail below.
If a data register has a logical value of zero, the corresponding NFET N
2
is turned off. In this case, if the corresponding read word line is selected, i.e., the corresponding NFET N
1
is turned on, and the corresponding read bit line is coupled to an equivalent diffusion capacitance of the NFET N
2
, which can be modeled as a capacitance C
2
. This diffusion capacitance C
2
is thus coupled in parallel with the capacitance C
1
of the pre-charged read bit line. The charge Q will then be shared by capacitance C
2
and capacitance C
1
. Consequently, the voltage of the read bit line will droop below V
DD
. However, since C
1
typically has a capacitance value much greater than C
2
, the voltage droop caused by a single C
2
is sufficiently small that the voltage on the read bit line will remain high enough for the output of the read bit line to reflect the stored data of the data register being read.
However, during a test mode, there can be a multi-hot condition, i.e., two or more read word lines may be selected. If more than one data registers along a read bit line have a value of zero, several diffusion capacitances C
2
will be coupled to the read bit line. The charge Q initially placed on the read bit line during the precharge phase will be shared by C
1
and multiple C
2
's, significantly lowering the read bit line voltage. The final voltage V
final
on the read bit line for a multi-hot condition with each corresponding data register having a value of zero can be calculated as:
V
final
=
V
DD
·
C
1
C
1
+
x
·
C
2
,
where x is the number of transistors N
1
turned on. If the voltage droop is severe enough, an erroneous result may occur.
The voltage droop caused by a multi-hot condition is especially serious in a low-voltage system in which Vdd is low, since even a comparatively small percentage drop in Vdd may reduce the voltage to below the threshold level of an output inverter
150
.
Therefore, there is a need for a technique to reduce the effect of charge sharing in a register array during a multi-hot condition.
SUMMARY OF THE INVENTION
The present invention provides a register array system and a method for reading the register array system that essentially eliminate the problem of charge sharing in a multi-hot condition.
In one embodiment of the present invention, the register array system comprises a first number of rows by a second number of columns of data registers, a read word line corresponding to each row of data registers, a read bit line corresponding to each column of data registers, and a pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The register array system further comprises a first logic device corresponding to each row of data registers, receiving as inputs a clock signal and a read enable signal for the row of data registers, and having an output connected to the read word line corresponding to the same row of data registers. The register array system further comprises a second logic device corresponding to each data register in each row of data registers, and having a first input coupled to the data register and a second input connected to the read word line corresponding the row of data registers. The second logic device corresponding to a data register produces an output that turns on or off the pull down device corresponding to the same data register.
In one embodiment of the present invention, the first logic device corresponding to a row of data r
Kalyanasundharam Vydhyanathan
Naini Ajay
Fenwick & West LLP
Fujitsu Limited
Lebentritt Michael S.
Phung Anh
LandOfFree
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