Read operation of multi-port memory device

Details Read operation of multi-port memory device Read operation of multi-port memory device

2007-09-20

2010-02-09

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189150, C365S189160, C365S233100

Reexamination Certificate

active

07660168

ABSTRACT:
A multi-port memory device includes a plurality of ports, a plurality of bank control units, a plurality of banks, a read clock generation unit, and a data transmission unit. Each of the banks is connected to a corresponding one of the bank control units. The read clock generation unit generates a read clock toggling for four clocks in response to a read command. The data transmission unit transmits a read data from the banks to a corresponding one of the ports in response to the read clock. Every bank control unit is connected to all of the ports.

REFERENCES:
patent: 5375089 (1994-12-01), Lo
patent: 6714477 (2004-03-01), Nakayama et al.
patent: 7123538 (2006-10-01), Yamauchi et al.
patent: 1755606 (2006-04-01), None
patent: 2000-339999 (2000-12-01), None
patent: 2002-109884 (2002-04-01), None
patent: 1019970075449 (2001-02-01), None
patent: 10-2006-0032948 (2006-04-01), None

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