Read only memory having bias circuits

Details Read only memory having bias circuits Read only memory having bias circuits

1999-09-02

2000-06-06

Mai, Son

Static information storage and retrieval

Read/write circuit

Signals

365104, 365203, G11C 1700

Patent

active

060727349

ABSTRACT:
The disclosure is a read only memory having a memory cell array formed of a plurality of memory cells coupled to wordlines and bitlines, the bitlines being alternately connected to main bitlines and ground lines. The invented read only memory include an address transition detection signal source. It also includes a first delay circuit for receiving the address transition detection signal and for generating a first discharge signal for driving the ground lines. It also includes a second delay circuit for receiving the address transition detection signal and for generating a second discharge signal for driving the main bitlines. It also includes a first pulse circuit for receiving the first discharge signal and for generating a first precharge signal for driving the ground lines. Finally, it includes a second pulse circuit for receiving the second discharge signal and for generating a second precharge signal for driving the main bitlines. The timing of the delay and pulse circuits are such that the trailing edges of the first and second discharge signals are substantially simultaneous with one another and that the leading edges of the first and second precharge signals are substantially simultaneous with one another. The result is that the voltage levels on a selected main bitlines and a non-selected ground line are substantially identical, permitting the memory to be read reliably.

REFERENCES:
patent: 5241497 (1993-08-01), Komarek
patent: 5566129 (1996-10-01), Nakashima et al.
patent: 5600586 (1997-02-01), Lee
patent: 5625586 (1997-04-01), Yamasaki et al.
patent: 5757709 (1998-05-01), Suminaga et al.
patent: 5790450 (1998-08-01), Nishizaka et al.
Mikiro Okada et al., "16Mb ROM Design Using Bank Select Architecture", Integrated Circuits Group, Sharp Corporation, Japan, pp. 85-86.

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