Read only memory device equipped with output data buffer circuit

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365194, 365203, 365206, 365208, G11C 700

Patent

active

053093976

ABSTRACT:
A read only memory device firstly charges a digit line and, thereafter, couples the digit line with a discharging line so as to see whether or not a selected memory cell location provides a current path to the discharging line, wherein an n-channel enhancement type transfer transistor is coupled between a column selector and an output driver circuit for introducing time delay into undesirable voltage fluctuation due to noises on the discharging line, thereby preventing an output data signal from undesirable inversion.

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