Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-08-06
2001-04-03
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, 43, C257S390000
Reexamination Certificate
active
06211019
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a read-only memory cell device and a method for the production of a read-only memory cell device including a substrate formed of semiconductor material and having a main area, memory cells disposed in the vicinity of the main area in matrix form in columns and rows in a cell field, each memory cell having in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode, the MOS transistors of a column connected in series one after the other, each column connected to a bit line and the gate electrodes of the MOS transistors of a row connected to a word line.
Read-only memory cell devices of the generic type are disclosed, for example, in an article entitled “A 256 kbit ROM with Serial ROM Cell Structure”, by R. Cuppens and L. H. M. Sevat, in IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 3, June 1983, pages 340-344; and in an article entitled “High Density CMOS Read-Only Memories for a Handheld Electronics Language Translator”, by S. Kamuro et al., in IEEE Transactions on Consumer Electronics, Vol. CE-27, No. 4, November 1981, pages 605 et seq. In those read-only memories a serially interconnected memory cell configuration having a NAND circuit configuration is used for the purpose of increasing the storage density per unit area. The formation of contact holes in the memory cell field can be avoided, as a result of which a very small ROM memory cell can be produced. However, it is necessary to accept a reduced access speed as compared with read-only memories which have a parallel-connected memory cell configuration with a NOR circuit configuration. However, for the purpose of storing considerable volumes of data in many of today's electronic systems, the primary feature is a maximum storage density. That is necessary in order to be able to accommodate a maximum number of memory cells per unit area with sufficiently low process costs to realize a corresponding cost advantage. In the case of the known ROM or OTP memory cells, it is possible to achieve a cell size of 5F
2
with customary CMOS technologies using a serial circuit configuration of the memory cells in a NAND cell configuration. F denotes the smallest structure size that can be produced or resolved with the respective technology.
Moreover, further-developed read-only memory cell devices and methods for their production have been disclosed, for example, in German Patent DE 44 34 725 C1 and in German Published, Non-Prosecuted Patent Application DE 44 37 581 A1 having the same corporate assignee as the instant application. In those devices, memory cell transistors are constructed in a configuration which is vertical with respect to the main area of the silicon substrate. Such read-only memory cell devices, which are more advanced but are more complicated to produce, have a storage density of 2F
2
cells.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a read-only memory cell device and a method for the production of a read-only memory cell device, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and which afford simpler and more cost-effective production in conjunction with a high packing density of the memory cells and a high yield.
With the foregoing and other objects in view there is provided, in accordance with the invention, a read-only memory cell device, comprising a substrate formed of semiconductor material and having a main area; bit lines and word lines; memory cells disposed in matrix form in columns and rows in a cell field in the vicinity of the main area, each of the memory cells having at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode, the MOS transistors of a column connected in series one after the other, each column connected to a bit line and the gate electrodes of the MOS transistors of a row connected to a word line; source/drain webs running substantially parallel to one another at a predetermined spacing, electrically insulated from one another, produced from the semiconductor material of the substrate and having a longitudinal direction and a predetermined web depth starting from the main area of the substrate, the source and drain regions of the MOS transistors of a column formed in the source/drain webs; and the word lines for connection of the gate electrodes of the MOS transistors running transversely relative to the longitudinal direction of the source/drain webs.
Accordingly, an essential feature of the invention is that of providing a memory cell configuration which has crossing source/drain and gate paths and the possibility of a cell size of 1F
2
instead of the heretofore maximum possible storage density of 2F
2
, thereby enabling precisely one memory cell to be realized per base area F
2
.
In accordance with another feature of the invention, the drain region, formed in the main area of a source/drain web, of an MOS transistor of a column, simultaneously constitutes the source region of that MOS transistor of the same column which is directly adjacent on the source/drain web. In this way, the memory cells can be constructed in a so-called NAND circuit configuration, which enables a particularly high storage density in conjunction with a cell structure that is technologically simple to produce.
In accordance with a further feature of the invention, the ratio of the web width which is measured on the main area transversely with respect to the longitudinal direction of the web, to the spacing between the source/drain webs, is about 20% to 40%, in particular about one third, of the resolvable structure size F. In the case of a maximum structure size F of about 1 &mgr;m, which is essentially predetermined by the resolution of the photographic technique being used, the width of the source/drain web is preferably about 0.3 &mgr;m given a spacing between the source/drain webs corresponding to the resolvable structure size F, that is to say likewise about 1 &mgr;m. With a planar structure of the memory cells, these dimensions yield the maximum possible memory cell density, with conventional lithographic technologies, of precisely one memory cell per base area F
2
.
In accordance with an added feature of the invention, the structure of the read-only memory cell device has serially connected memory transistors in a NAND cell configuration, and each of the MOS transistors of a memory cell which are formed on the main area of the source/drain webs is programmed as a depletion-mode transistor or an enhancement-mode transistor.
In accordance with an additional feature, the invention is suitable both for the production of one-time electrically programmable read-only memories, in which the gate dielectric has, in particular, an ONO forming material (a so-called OTP or One-Time-Programmable memory) or, as an alternative, for the production of mask-programmable read-only memories (a so-called mask-programmable ROM or Read-Only-Memory), in which the gate dielectric has, in particular, a gate oxide.
In accordance with yet another feature of the invention, the space region between the source/drain webs is filled with an electrically insulating material, in particular a material containing SiO
2
.
With the objects of the invention in view, there is also provided a method for the production of a read-only memory cell device including a substrate formed of semiconductor material and having a main area, memory cells disposed in the vicinity of the main area in matrix form in columns and rows in a cell field, each memory cell having at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode, the MOS transistors of a column connected in series one after the other, each column connected to a bit line and the gate electrodes of the MOS transistors of a row connected to a word line, which comprises forming the source and dra
Bertagnolli Emmerich
Klose Helmut
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Luu Pho
LandOfFree
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