Read-only memory cell arrangement and method for its production

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438276, 257332, 257391, H01L 218246, H01L 27112

Patent

active

059207787

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

Memories into which data are written permanently in digital form are required for many electronic systems. Such memories are called, inter alia, read-only memories.
Plastic discs, so-called compact discs, which are coated with aluminium are in widespread use as read-only memories for large quantities of data, in particular the digital recording of music. These discs have two different kinds of point-like depressions in the coating, which are assigned to the logic values zero and one. The information is stored digitally in the arrangement of these depressions.
In order to read the data which are stored on a compact disc, the disc is mechanically rotated in a read apparatus. The point-like depressions are scanned via a laser diode and a photocell. Typical scanning rates in this case are 2.times.40 kHz. Approximately 5 Gbits of information can be stored on one plastic disc.
The read apparatus has moving parts which undergo mechanical wear, require comparatively large volumes, allow only slow data access and consume a great deal of power. The read apparatus is furthermore sensitive to vibration and can thus be used only to a limited extent for mobile systems.
Semiconductor-based, in particular silicon-based, read-only memories are frequently used for the storage of smaller amounts of data. When the memory cell arrangement is read, the individual memory cells are selected via a word line. The gate electrode of the MOS transistors is in each case connected to a word line. The input of each MOS transistor is connected to a reference line, and the output to a bit line. An assessment is carried out during the reading process to determine whether or not any current is flowing through the transistor. The logic values zero and one are assigned accordingly.
Technically, the storage of zero and one is brought about in the case of these read-only memories by no MOS transistor being produced, or no conductive connection to the bit line being produced, in memory cells in which the logic value assigned to the state "no current flow through the transistor" is stored. Alternatively, the two logic values can be produced by MOS transistors which have different operating voltages as a result of different implantations in the channel region.
These known silicon memories usually have a planar construction. In consequence, a minimal surface area, which is about 6 to 8 F.sup.2, is required per memory cell, F being the smallest producible structure size in the respective technology. Planar silicon read-only memories are thus limited to memory densities of about 0.9 bit/.mu.m.sup.2 when using 0.4 .mu.m technology.
U.S. Pat. No. 4,954,854 discloses the use of vertical MOS transistors in a read-only memory. The surface of the silicon substrate is for this purpose provided with hole-like trenches against which a source region abuts at the base, against which a drain region, surrounding the trench, abuts at the substrate surface, and along whose flanks a channel region is arranged. The surface of the trench is provided with a gate dielectric, and the trench is filled with a gate electrode. Zero and one are distinguished in this arrangement by no trench being etched and no transistor being produced for one of the logic values. Neighbouring memory cells are insulated from one another by insulating structures arranged laterally with respect to them.


SUMMARY OF THE INVENTION

The object of the invention is to provide a semiconductor-based read-only memory cell arrangement, in the case of which an increased memory density is achieved and which can be produced with a small number of production steps and with a high yield. A further object is to provide a method for the production of such a memory cell arrangement.
In the read-only memory cell arrangement according to the invention, a cell array having memory cells is provided in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. In this case, a first logic value is respectively stored in first memory cells

REFERENCES:
patent: 4630237 (1986-12-01), Miura et al.
patent: 4663644 (1987-05-01), Shimizu
patent: 4954854 (1990-09-01), Dhong et al.
patent: 5385852 (1995-01-01), Oppermann et al.
patent: 5744393 (1998-04-01), Risch et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Read-only memory cell arrangement and method for its production does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Read-only memory cell arrangement and method for its production, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read-only memory cell arrangement and method for its production will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-906971

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.