Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-21
2002-10-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S130000, C438S276000, C438S128000, C257S318000, C257S321000, C257S316000, C257S390000, C365S185220, C365S175000, C365S174000, C365S201000, C365S189011
Reexamination Certificate
active
06472275
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a read-only memory (ROM) such as a mask ROM; and especially to ROM employing NAND type memory cell structure.
BACKGROUND OF THE INVENTION
A conventional mask ROM includes a memory cell matrix provided on a semiconductor substrate, the memory cell matrix being of MOS transistors. In accordance with the type of binary data stored therein, enhancement type transistors (EMOS) and depression type transistors (DMOS) are selectively formed on the semiconductor substrate. When the MOS transistor is of N-type, EMOS and DMOS have threshold values of positive and negative, respectively.
In a ROM with NAND type memory cell structure, when a memory cell line extending along a bit line is selected and a MOS transistor corresponding to a word line is selected, non selected word lines keep positive in electric potential. The MOS transistors connected to such non selected word lines are in a closed condition, regardless of type of the transistor, enhancement type or depression type.
On the other hand, the selected word lines are in zero voltage condition. When the MOS transistor connected to one of the selected word lines is of enhancement type, the MOS transistor turns on or opened. When the MOS transistor connected to one of the selected word lines is of depression type, the MOS transistor turns off or closed. In other words, when the selected MOS transistor is of enhancement type, no electrical current flows through the corresponding bit line. When the selected MOS transistor is of depression type, electrical current flows through the corresponding bit line.
It can be determined whether the selected (or addressed) transistor is DMOS or EMOS by detecting the current flowing through the corresponding bit line. In other words, it can be determined whether the selected memory cell stores “1” or “0”.
According to such a mask ROM, binary data are written to the memory cell matrix by ion implantation process, after the fabrication of the MOS transistors are completed. For example, enhancement type of transistors are firs formed for all the memory cell regions, and then some memory cells are changed to depression type by ion implantation process. Therefore, the fabrication steps of the ROM become complicated. Since the ion implantation process is carried out after the MOS transistor fabrication is completed, the ion implantation process may affect to other circuits on the same semiconductor substrate. In some cases, the circuit design of the ROM must be changed fundamentally to avoid the affection of the ion implantation.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a read-only memory which can be fabricated without impurity implantation after the fabrication of transistors are completed.
Another object of the present invention is to provide a method for fabricating a read-only memory in which no impurity implantation is carried out after the fabrication of transistors are completed.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.
The conducting regions always keep a closed or conducting condition regardless of selected or non-selected as the same as depression type MOS transistors. Therefore, when one of the field effect transistors is selected or addressed, the corresponding bit line is opened or disconnected. On the other hand, when one of the conducting regions is selected or addressed, the corresponding bit line is closed or connected. It can be determined whether the selected (or addressed) transistor is field effect transistor or conducting region by detecting the current flowing through the corresponding bit line. In other words, it can be determined whether the selected memory cell stores “1” or “0”.
The conducting regions are provided instead of depression type of MOS transistors in a conventional ROM. The conducting regions may be formed by thermal diffusion of impurities or impurity implantation process, which can be carried out simultaneously with forming source and drain of the field effect transistors. As a result, it is unnecessary to carry out an ion implantation process just for writing binary data in the memory cell matrix.
According to the present invention, no ion implantation process is carried out just for writing binary data into a memory cell matrix, so that the fabrication steps can be simplified, and thereby costs for fabricating read-only memories can be decreased. Because no ion implantation process is carried out after the MOS transistor fabrication is completed, the ion implantation process does not affect to other circuits on the same semiconductor substrate. Therefore, the circuitry of the ROM can be designed with more degree of freedom as compared to the conventional technology.
The read-only memory according to the present invention may be a NAND type mask ROM.
The read-only memory according to the present invention may further includes a current regulating circuit provided within each of memory cell lines corresponding to the bit lines to regulate the amount of electrical current flowing through the memory cell line. The degree of regulation by the current regulating circuit is determined in accordance with the number of the conducting regions provided in the corresponding memory cell line.
The conducting regions have lower resistance relative to the field effect transistors. The more current flows through a bit line in which the more conducting regions are formed in the corresponding memory cell line. Electric current flowing through a selected bit line is converted to the corresponding voltage and detected. When such a voltage increases, detecting time for comparing with a reference voltage increases as well; and therefore, the access time becomes longer. The current regulating circuit prevents increasing of the bit line current, which undesirably changes the access time of the ROM. Electric current flowing through the bit line is uniformed, and therefore, the access time of the ROM may be shortened.
The current regulating circuits may be switching elements formed from field effect transistors, each of which is formed between the corresponding memory cell line and bit line.
The switching element may be designed to have an optimum gate length that is defined in response to the number of the conducting region(s) formed within the corresponding memory cell line. Such a switching element may be designed to have a longer gate length when a large number of conducting regions are formed with in the corresponding memory cell line. According to the switching elements, irregular of current flowing through the bit lines is prevented.
The switching elements may be designed to have an optimum gate width that is defined in response to the number of the conducting region(s) formed within the corresponding memory cell line. Such a switching element may be designed to have a narrower gate width when a large number of conducting regions are formed with in the corresponding memory cell line.
The field effect transistors, forming the memory cell matrix, may be enhancement type field effect transistors, in which sour
Katoh Teruo
Mizuhashi Hiroshi
Oki Electric Industry Co. Ltd.
Smith Matthew
Volentine & Francos, PLLC
Yevsikov V.
LandOfFree
Read-only memory and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Read-only memory and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Read-only memory and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2938571