Read only memory

Details Read only memory Read only memory

1992-10-23

1994-04-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

36518905, 36518911, G11C 900

Patent

active

053031946

ABSTRACT:
A read only memory for eliminating the unpredictable logic states of bit lines in order to prevent the generation of false logic states while avoiding increase in power dissipation. The memory comprises bit lines, sense amplifiers, bit data holding device and reset device. The logic state of a given bit line is output by the applicable sense amplifier as bit data. In either the High or the Low state, that bit line enters a floating state that can vary with precharged electric charge. The potentially destabilizing state is circumvented by the bit data holding device which prevents the logic state of the bit line from becoming unpredictable. During precharging, the reset device resets the bit line state held by the bit data holding device. This prevents a through current from flowing even if the logic state of the applicable bit line changes.

REFERENCES:
patent: 4603403 (1986-07-01), Toda

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