Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-08-30
2001-10-23
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080
Reexamination Certificate
active
06307790
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to read data paths in a memory device.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices typically include one or more arrays of memory cells that store data. The data is either read from or written to the memory cell using data communication connections. Some example memory devices include but are not limited to random access memories (RAM), dynamic random access memories (DRAM), Synchronous DRAM (SDRAM), static RAM (SRAM), and non-volatile memories such as FLASH.
During production of the memory devices, the individual memory cells need to be tested. Thus, data is written to the memory cells and then the data is read from the memory. As the density of the memory arrays increase, the time needed to fully test the memory array also increases.
One technique that can be used to decrease test time is data compression. That is, data read from multiple memory cells are compressed into a smaller number of data bits. Thus, less data communication connections (DQ's) are required for a given number of memory cells when implementing data compression. The data compression circuitry is included in the memory device and adds overhead to the data read and write paths. This overhead can decrease operating speeds during normal, non-test operations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device having data compression circuitry while maintaining suitable operating speeds during normal, non-test operations
SUMMARY OF THE INVENTION
The above-mentioned problems with memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises an array of memory cells, a plurality of data output buffers to provide data from the array to external nodes, and first and second parallel data paths between the array and the plurality of data output buffers. The first data path comprises compression logic to compress the data from the array to a portion of the plurality of data output buffers.
In another embodiment, a memory device comprises a memory array with y-banks of memory cells arranged in rows and columns, x-output buffers coupled to the y-banks to provide data on x-output nodes, and a first set of data paths coupled between the y-banks and the x-output buffers to couple data from x-columns of one of the y-banks to the x-output buffers. A second set of data paths are coupled between the y-banks and the x-output buffers. The second set of data paths comprise compression logic to simultaneously couple x-columns from the y-banks to a portion of the x-output buffers. Multiplex circuitry is coupled to the output buffers and the first and second sets of data paths to selectively couple the first or second data path to the output buffers.
A method of operating a memory is described. The method comprises initiating a read operation, coupling first data from an array to outputs through a first data path during the read operation, initiating a test operation and coupling second data from the array to the outputs through a second data path during the test operation. The first and second data paths are coupled in parallel and the second data path comprises compression circuitry.
REFERENCES:
patent: 5463581 (1995-10-01), Koshikawa
Nobunaga Dean
Roohparvar Frankie F.
Fears Terrell W.
Fogg Slifer & Polglaze, P.A.
Micro)n Technology, Inc.
Slifer Russell D.
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