Read circuit of dynamic random access memory

Details Read circuit of dynamic random access memory Read circuit of dynamic random access memory

1991-11-26

1994-03-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

365226, 36518911, 365205, G11C 700

Patent

active

052914500

ABSTRACT:
In a dynamic random access memory including a plurality of memory read circuit arrays, a sense amplifier has a circuit wherein a first switch (or a pair of first switches) and a pair of second switches connected in series to the first switch are connected between the common data lines and the common source line of a second precharger. The first switch is controlled according to the potential of the bit lines precharged by a first precharger, while the second switches are controlled according to the address signal. Further, a third switch is provided to connect the common source line to an activation potential for the common source line in the memory array not selected. A second precharger precharges the common source line in a memory array not selected to a second precharge potential and the common data lines in a memory array not selected to a third precharge potential during the time when the common source line and the common data lines are not selected. The first, second and the third precharge potentials are set so as to prevent a through current through the third switch. Alternatively, the third switch may be omitted by providing appropriate precharge potentials.

REFERENCES:
patent: 4780852 (1988-10-01), Kajigaya et al.
patent: 4858190 (1989-08-01), Yamaguchi et al.
patent: 4875192 (1989-10-01), Matsumoto
patent: 4893277 (1990-01-01), Kajigaya et al.
K. Yanagisawa et al., ESSCIR, pp. 184-187.
Y. Nakagome et al., 1990 Symposium on VLSI Circuits, pp. 17-18.

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