Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1996-08-02
2000-05-23
Tse, Young T.
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375376, H04L 7033
Patent
active
060673354
ABSTRACT:
The present invention discloses a fully integrated data synchronization circuit for a disk drive read channel system. The data synchronization system comprises dual data synchronizers to provide read reference clocks. Dual PLL circuits are coupled to the data synchronizers to provide a stable reference frequency to data synchronizers. One of the two data synchronizers is used to obtain leading edge data, while the other is for trailing edge data. Each PLL circuit comprises a phase detector, a charge pump, and a VCO. A loop filter is used in conjunction with a charge pump to control loop characteristics of the PLLs. In an idle mode, one of the PLLs is used as a time base generator to provide a stable reference frequency to data synchronizers. Once data synchronizers achieve lock using the stable reference frequency and switch over to read data, the time base generator PLL is switched over to function as a data synchronizer PLL in a read mode. Thus, one of the PLLs is used as both time base generator and data synchronizer PLL, thereby eliminating the need for extra PLL circuitry and requiring only two PLL circuits to support time base generation and data synchronization.
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patent: 5528638 (1996-06-01), Rajivan
Kobayashi Hiroshi
Yamanoi Koyu
Yamauchi Toshio
Brady III Wade James
Silicon Systems Inc.
Swayze, Jr. W. Daniel
Telecky Jr. Frederick J.
Tse Young T.
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