Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1994-02-25
1995-02-07
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365194, 365207, 3652335, 327 55, G11C 700
Patent
active
053880757
ABSTRACT:
A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.
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Dinh Son
Thunderbird Technologies, Inc.
Yoo Do Hyun
LandOfFree
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