Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-14
2004-02-17
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S687000
Reexamination Certificate
active
06693030
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a moralization method for manufacturing semiconductor devices. More particularly, the present invention relates to precleaning of submicron features prior to moralization.
2. Background of the Related Art
Sub-half micron multilevel moralization is one of the key technologies for the next generation of very large scale integration (VIS). The multilevel interconnects that lie at the heart of this technology require polarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines or other features. Reliable formation of these interconnect features is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
The increase in circuit densities primarily results from a decrease in the widths of vias, contacts and other features as well as a decrease in the thickness of dielectric materials between these features. Cleaning of the features to remove contaminants prior to moralization is required to improve device integrity. The decrease in width of the features results in larger aspect ratios for the features and increased difficulty in cleaning the features prior to filling the features with metal or other materials. Failure to clean the features can result in void formation within the features or an increase in the resistance of the features. Therefore, there is a great amount of ongoing effort being directed at cleaning small features having high aspect ratios, especially where the ratio of feature height to width is 4:1 or larger.
The presence of native oxides and other contaminants within a small feature typically results in voids by promoting uneven distribution of the depositing metal. The native oxide typically forms as a result of exposing the exposed film layer/substrate to oxygen. Oxygen exposure occurs when moving substrates between processing chambers at atmospheric conditions, or when the small amount of oxygen remaining in a vacuum chamber contacts the wafer/film layer, or when a layer is damaged by etching. Other contaminants within the features can be sputtered material from an oxide over-etch, residual photoresist from a stripping process, leftover polymer from a previous oxide etch step, or redeposited material from a preclean sputter etch process. The native oxide and other contaminants create regions on the substrate which interfere with film formation, by creating regions where film growth is stunted. Regions of increased growth merge and seal the small features before regions of limited growth can be filled with the depositing metal.
The presence of native oxides and other contaminants also can increase the via/contact resistance and can reduce the electro migration resistance of small features. The contaminants can diffuse into the dielectric layer, the sublayer, or the deposited metal and alter the performance of devices which include the small features. Although contamination may be limited to a thin boundary region within the features, the thin boundary region is a substantial part of the small features. The acceptable level of contaminants in the features decreases as the features get smaller in width.
Precleaning of features using sputter etch processes is effective for reducing contaminants in large features or in small features having aspect ratios smaller than about 4:1. However, sputter etch processes can damage silicon layers by physical bombardment, sputter deposit Si/SiO
2
onto sidewalls of the features, and sputter metal sublayers, such as aluminum or copper, onto sidewalls of the features. For larger features, the sputter etch processes typically reduce the amount of contaminants within the features to acceptable levels. For small features having larger aspect ratios, sputter etch processes have not been as effective in removing contaminants within the features, thereby compromising the performance of the devices which are formed.
Preclean by sputter etch process is particularly unsuitable for features with copper substrate. It is because of the ease of diffusion of sputtered Cu through the dielectric sidewalls. This diffusion is especially true for TEOS, thermal oxide and some low K dielectric materials. Therefore, a new preclean process without any bias on the substrate is needed for a Cu preclean application.
Wet chemical cleaning processes have been developed to clean submicron features prior to moralization without the damage or contamination seen in sputter etch processes. The wet chemical processes typically include treatment of the feature with hydrofluoric acid (HF) to remove native oxides. Various other wet chemical processes can be used depending on the contaminants remaining in the features. The wet chemical cleaning processes can be combined with dry cleaning processes. However, the addition of wet chemical cleaning steps to remove trace amounts of contaminants from the features substantially increases the overall process time for moralization.
A soft etch cleaning process for submicron features is described by Sumi et al., “New Contact Process Using Soft Etch for Stable Ohmic Characteristics and its Application to 0.1 micron CMOS Devices”, IEDM 94-113 et seq. The soft etch process uses an inductively coupled plasma of argon to remove native oxides from a silicon underlayer. The process does not avoid resputtering of materials from the bottom to the sidewalls of the contact hole.
A dry cleaning process for submicron features is described by Taguwa et al., “Low-Contact Resistance Moralization for Gigabit Scale DRAMs Using Fully-Dry Cleaning by Ar/H
2
ECR Plasma”, IEDM 95-695 et seq. The dry cleaning process preferably cleans the features with an Electron Cyclotron Plasma containing a mixture of argon and hydrogen prior to chemical vapor deposition of titanium. The cleaning process reduces bombardment by Ar, removes native oxides from a silicon underlayer, and promotes formation of a uniform TiSi
x
, layer between the silicon underlayer and the deposited titanium. However, addition of H
2
to Ar in the cleaning process does not completely eliminate resputtering of materials within the features.
For sub-quarter micron features having high aspect ratios, resputtering of material from the bottom to the sidewalls of the feature during dry cleaning results in a significant narrowing of the feature and a corresponding increase in resistance of the feature which impairs device performance. The known dry cleaning processes are not effective in removing contaminants from the features without redepositing material on the sidewalls of the features. Therefore, there remains a need for a cleaning process for small features which effectively cleans the feature without leaving contaminants in the feature.
SUMMARY OF THE INVENTION
The present invention provides a method for precleaning features on a semiconductor substrate to remove contaminants prior to moralization. The method includes removal of oxides from the bottom of contacts without damaging the underlying layer, including the removal of SiO
2
, aluminum oxide or copper oxide from the bottom of vias without redeposition of the material onto sidewalls, the removal of a thin layer of damaged silicon from the bottom of contact holes, and the removal of contaminants from the sidewalls of the features. The precleaning of the features preferably includes a first step wherein contaminants are removed with radicals from a remote plasma of a reactive cleaning gas, and an optional second step wherein native oxides remaining in the features are reduced by exposure to hydrogen radicals. The plasma of the cleaning gas is preferably generated by a remote plasma source to provide a soft etch which does not damage or resputter the sublayers at the bottom of the features.
Following the first or both precleaning steps, the features can be filled with metal by available techniques which typically include depositing a barrier/liner layer on the exposed dielectric surfaces using physical vapor deposition
Chen Liang-Yuh
Mosely Roderick Craig
Subrahmanyan Suchitra
Applied Materials Inc.
Ho Hoai
Moser Patterson & Sheridan LLP
Vu David
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