Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-12
2002-08-20
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S263000, C438S269000
Reexamination Certificate
active
06436778
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor device. In particular, the present invention relates to a method and process for manufacturing a non-volatile memory device.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of large blocks of memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode within which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing negative electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when negative charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state. Data resides in a certain logic state on the floating-gate electrode. During a read operation, selected data from a selected floating-gate electrode can be output to an external communication unit using a bit-line.
In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating-gate by an overlying control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied on the control-gate electrode is coupled to the floating-gate electrode. The flash EEPROM device is programmed by applying a high positive voltage to the control-gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating-gate electrode. The flash EEPROM device is erased by grounding the control-gate electrode and applying a high positive voltage through either the source or drain region of the enhancement transistor. Under erase voltage conditions, electrons are removed from the floating-gate electrode and transferred into either the source or drain regions in the semiconductor substrate.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Many of the foregoing research goals can be addressed through development of materials and processes for the fabrication of the floating-gate electrode. While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, fabricating a tunnel oxide within a memory cell presents several challenges. For example, the reliability of the tunnel oxide can be problematic. The problems with the reliability of the tunnel oxide are often associated with charge trapping and oxide damage during the programming and erasing cycles within the memory cell. The damaged tunnel oxide may cause memory data retention problems and may also result in the failure of the memory cell. In order to improve the reliability of the tunnel oxide, an oxynitridation process is often employed to form the tunnel oxide.
There are several problems that occur with the above-described method for fabricating a memory cell. One problem is that during the oxynitridation process, nitrogen, which is introduced into the tunnel oxide, can also enter into and contaminate the gate oxide in the peripheral gate region. Nitrogen introduced into the semiconductor substrate will often form a bond with the silicon atoms in the semiconductor substrate, and thus, make it very difficult to remove the nitrogen from the semiconductor substrate. For example, the nitrogen that is contaminating the semiconductor substrate cannot be effectively removed by using a conventional hydrofluoric acid etch process. Additionally, the presence of the contaminate nitrogen contributes to non-uniform oxide growth during a subsequent growth of a gate oxide layer. Since the oxynitridation process degrades the characteristics of the gate oxide layer in a peripheral gate region of the memory cell, the oxynitridation approach is less attractive for manufacturing memory cells. Accordingly, advances in memory cell fabrication technology are necessary to improve the reliability of the tunnel oxide without affecting the reliability of the gate oxide layer.
BRIEF SUMMARY
The present invention is for a process for fabricating a semiconductor device, and more preferably, a memory device. Although the following description is described with respect to fabricating an EEPROM device, it will be recognized by those skilled in the art that the following description can not only be applied to fabricating any non-volatile memory device, such as a one-bit or two-bit EEPROM device, but to any semiconductor device as well, such as a capacitor, a diode, a resistor, an amplifier, a memory chip, a microchip, an integrated circuit, a transistor, a digital signal processor, and a logic chip.
According to one aspect of the present invention, a process for fabricating a semiconductor device is provided. The process includes providing a semiconductor substrate having a core region and a peripheral gate region. The semiconductor substrate has at least one shallow trench isolation region and at least one nitrogen-contaminated region in the peripheral gate region. A tunnel oxide layer overlies the semiconductor substrate and a first polysilicon layer overlies the tunnel oxide layer in the core region. An ONO layer overlies the first polysilicon layer in the core region. The process further includes growing a sacrificial oxide layer overlying the nitrogen-contaminated region in the peripheral gate region, wherein oxygen from within the sacrificial oxide layer diffuses into the nitrogen-contaminated region and forms silicon dioxide. By allowing oxygen from within the sacrificial oxide layer to diffuse into the nitrogen-contaminated region and form silicon dioxide, the nitrogen can be removed from within the semiconductor substrate by removing the silicon dioxide.
REFERENCES:
patent: 5661055 (1997-08-01), Hsu et al.
patent: 5861347 (1999-01-01), Maiti et al.
patent: 6117783 (2000-09-01), Samll et al.
patent: 6143608 (2000-11-01), He et al.
patent: 6147002 (2000-11-01), Kneer
patent: 6153935 (2000-11-01), Edelstein et al.
patent: 6177312 (2001-01-01), He et al.
patent: 6225167 (2001-05-01), Yu et al.
patent: 6306707 (2001-10-01), Foster et al.
Fang Hao
He Yue-song
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Lebentritt Michael S.
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