Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-16
2001-05-08
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S301000, C438S304000, C438S305000, C438S597000
Reexamination Certificate
active
06228731
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a metal silicon oxide field effect transistor, (MOSFET), device, featuring a self-aligned contact, (SAC), structure.
(2) Description of Prior Art
Static random access memory, (SRAM), cells are usually comprised of six MOSFET devices, preferably four NFET, (n channel), devices, and two PFET, (p channel), devices. In general, to decrease the cost of semiconductor chips, the cell size, or SRAM cells in this case, have to be decreased, to allow a greater amount of smaller semiconductor chips to be obtained from a specific size starting substrate, thus reducing the processing cost of each specific semiconductor chip, however with the now smaller SRAM cell, still supplying the device density and performance obtained with SRAM cells fabricated with larger features. Therefore to decrease SRAM cell size, the size of the PFET and NFET devices have to be reduced.
Micro-miniaturization, or the use of sub-micron features, obtained via optimization of specific fabrication disciplines, such as photolithography, and dry etching, have allowed the objective of smaller MOSFET devices, to be partially realized. However the use of specific design and structural innovations, such as a self-aligned opening, and a self-aligned contact, structure, have also contributed to the attainment of smaller SRAM devices, and cells, resulting in smaller, less expensive, SRAM semiconductor chips. When using conventional, or non-SAC hole opening procedures, to expose an underlying active device region, in a semiconductor substrate, the area of the active device region has to be increased to insure that this opening is fully landed on this region. This results in an increase in the designed dimension of the active device region, resulting in larger than desired cells, or chips. The SAC procedure however, as applied to an active device region such as a source/drain region, is comprised of an opening larger in diameter than the space between gate structures, where a source/drain region is located. This is accomplished via selective reactive ion etching, (RIE), procedures allowing the SAC opening to expose a portion of the top surface of insulator capped, gate structures, as well as the active device region, located between the insulator capped gate structures.
This invention will describe a procedure in which a SAC opening is made to a small designed space between insulator capped gate structures, with composite spacers on the sides of the gate structures. After definition of an active device region, such as a source/drain region, the space is enlarged via the removal of a component of the composite spacer. This process sequence allows the amount of designed active device area, needed to accommodate the SAC opening, to be reduced, however still allowing the needed amount of contact area when filled with an overlying SAC structure, due to the removal of a component of the composite spacer. Prior art, relating to SAC procedures, such as Chou et al, in U.S. Pat. No. 5,731,236, describe a SAC structure, however without the novel re-etched, or removed, spacer component, used in the present invention to increase device density.
SUMMARY OF THE INVENTION
It is an object of this invention to use SAC openings to expose active device regions in MOSFET devices.
It is another object of this invention to form an active device region in an area of a semiconductor substrate, defined by gate structures, and by composite spacers on the sides of the gate structures.
It is still another object of this invention to increase the area of the active device region, needed to accommodate a fully landed, SAC opening, by removing a component of the composite spacers, located on the sides of the gate structures, after formation of the active device region.
It is still yet another object of this invention to use polysilicon as the removable component of the spacers, located on the sides of the gate structures.
In accordance with the present invention a process for forming a SAC opening, to an active device region in a semiconductor substrate, located between gate structures, and featuring the removal of a polysilicon component of a composite sidewall spacer, located on the sides of the gate structures, performed to increase the area needed for the fully landed SAC opening, is described. After formation of silicon nitride capped, gate structures, on an underlying gate insulator layer, a lightly doped source/drain region is formed in a region of the semiconductor substrate, defined by the silicon nitride capped, gate structures. A thin silicon oxide layer is next formed on the surface of the lightly doped source/drain region, as well as on the sides of the silicon nitride capped, gate structures. A polysilicon layer is next deposited, followed by an anisotropic RIE procedure, creating a composite spacer, on the sides of the silicon nitride capped, gate structures, comprised of an overlying polysilicon shape, and an underlying, thin silicon oxide layer. After formation of a heavily doped source/drain region, in an region of the semiconductor substrate, defined by the silicon nitride capped, gate structures, and by the composite spacers, a thin silicon nitride stop layer, and an overlying, interlevel dielectric, (ILD), layer, are deposited. A self-aligned contact, (SAC), opening is then selectively formed in the ILD layer, and in the thin silicon nitride stop layer, exposing the thin silicon oxide layer, overlying the heavily doped source/drain region, located between the composite spacers, on the silicon nitride capped, gate structures. The SAC opening also exposes the top surface of the silicon nitride capped, gate structures, in a region adjacent to the space between the silicon nitride capped, gate structures. The polysilicon component, of the composite spacer, is then selectively removed, increasing the space between silicon nitride capped, gate structures. A thin insulator spacer is next formed on the sides of the SAC opening, followed by the creation of a metal structure, in the SAC opening, overlying, and contacting, the active device region, located between the silicon nitride capped, gate structures.
A second embodiment of this invention features the use of a composite spacer, comprised with an underlying a silicon nitride shape, and an overlying silicon oxide shape, defining the heavily doped source/drain region. During the SAC opening, and during the clean procedures, used to remove polymer generated during the SAC, dry etching procedure, the silicon oxide shape, of the composite spacer, is removed. The subsequent formation of a silicon nitride spacer, on the sides of the SAC opening, result in increased surface area at the bottom of the SAC opening, allowing increased contact between an overlying SAC metal structure, and the underlying active device region.
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Liaw Jhon-Jhy
Shen Yun-Hung
Ackerman Stephen B.
Bowers Charles
Saile George O.
Smoot Stephen W.
Taiwan Semiconductor Manufacturing Company
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