Rapid thermal annealing of doped polycrystalline silicon...

Details Rapid thermal annealing of doped polycrystalline silicon... Rapid thermal annealing of doped polycrystalline silicon...

1999-11-22

2001-03-20

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S770000, C438S787000, C438S788000, C438S279000, C438S307000, C438S308000

Reexamination Certificate

active

06204198

ABSTRACT:

FIELD OF THE INVENTION
The instant invention pertains to semiconductor device fabrication and processing and more specifically to a method of fabricating a doped polycrystalline silicon structure.
BACKGROUND OF THE INVENTION
An ever present trend in semiconductor device manufacturing involves the reduction in size of devices while trying to reduce the power consumed by devices. In more practical terms, this means shrinking each of the structures of the devices while trying to reduce the resistivity of structures that are subjected to any appreciable amount of electrical potential. One structure that is affected by these trends is the gate structure. With the shrinking of the device, the width of the gate structure is reduced. However, this reduction in width results in higher resistance of the gate structure because resistance of a structure is inversely proportional to the cross-sectional area of the structure. In order to reduce the resistance of these shrinking gate structures, the resistivity of the material which is used to form the gate structure, typically polycrystalline silicon (poly or polysilicon), needs to be reduced, because resistance of a structure is proportional to the resistivity of the material used to form the structure.
In an attempt to reduce the resistivity of gate structures which are made of polysilicon, many device manufacturers dope the polysilicon with either n-type dopants (for NMOS transistors) or p-type dopants (for PMOS transistors). The polysilicon can be in-situ doped as it is deposited or doped by implanting dopants after the polysilicon layer is formed over the semiconductor wafer. However, there are problems with doped polysilicon structures. One problem involves the migration of dopants during subsequent thermal processing (a higher temperature step is required after the dopants are put into the polysilicon so as to diffuse the dopants throughout the polysilicon film and render them electrically active). More specifically, dopants may escape from the doped polysilicon structure during these thermal processing steps. Hence, the full advantage in doping these films, i.e. the reduction of the resistivity of these films, is not fully achieved.
Two possible solutions to this problem involve either increasing the dopant concentration or using a furnace anneal. Placing more dopants into the polysilicon creates other problems, though, and may not solve the original problem because it may not be possible to place enough dopants into the polysilicon to replace those leaving. One of the problems with putting more dopants into the polysilicon is that the dopants may migrate from the polysilicon, through the underlying gate insulating material and into the substrate thereby degrading the transistor. Another problem is that unwanted change to the polysilicon grain structure may occur during the implantation of these large amount of dopants.
A furnace annealing process occurs for a long duration at an elevated temperature. While the annealing may take place in nitrogen ambient, an oxide layer forms on the surface of the wafers during loading in the furnace. The formation of an oxide layer on the polysilicon holds in the dopants. This type of process is contrary to another trend in the semiconductor device fabrication industry which involves the reduction of the “thermal budget” of the process to fabricate these devices. The “thermal budget” of a process is related to the various increased temperatures that the devices are subjected to in order to fabricate the devices and the time in which the devices are subjected to these elevated temperatures. Hence, the “thermal budget” can be reduced by either reducing the temperature of these elevated temperature steps or by limiting the duration of the elevated temperature steps. Since many fabrication steps require elevated temperatures, it may not be possible to significantly reduce the temperature of these steps. In response to this, many semiconductor device manufacturers are trying to use very high temperatures for very short periods in time. This type of processing is generically referred to as “rapid thermal processing” (RTP). More specifically, the RTP designation generally refers to: rapid thermal anneal (RTA), rapid thermal nitridation (RTN), and other rapid thermal steps. Typical RTA processing is accomplished in a vacuum or inert ambient and may reach temperatures as high as 1200C. Hence, this type of annealing will exacerbate the migration of dopants from the polysilicon layer.
In an attempt to rectify this problem, some manufacturers of semiconductor devices form a capping layer, consisting of silicon dioxide, on the polysilicon layer prior to the rapid thermal annealing of the polysilicon. However, this adds the additional processing steps of forming this thick layer (typically the layer is around 60 nm thick) and removing this layer. Examples of this process can be found in the following publications: R. A. Powell & R. Chow,
Dopant Activation and Redistribution in As
+
-
Implanted Polycrystalline Si by Rapid Thermal Processing
, JOURNAL OF ELECTROCHEMICAL SOCIETY: SOLID-STATE SCIENCE AND TECHNOLOGY 194-198 January 1985); and S. R. Wilson et. al.,
Fast Diffiusion of As in Polycrystalline Silicon During Rapid Thermal Annealing,
45(4) APPLIED PHYSICS LETTERS 464-466 (Aug. 15, 1984).
SUMMARY OF THE INVENTION
An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O
2
, O
3
, NO, N
2
O, H
2
O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer. More preferably, it has a thickness which is greater than 3 nm (more preferably greater than 2 nm). In an alternative embodiment, the thickness of the oxide layer is less than 20 nm (more preferably, less than 10 nm thick).
Another embodiment of the instant invention, is a method of fabricating a transistor having a conductive gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a gate insulating layer on the semiconductor substrate; forming a polycrystalline silicon layer on the gate insulating layer, the polycrystalline silicon layer is doped with a dopant; subjecting the transistor to a temperature of around 700 to 1100 C.in an oxidizing ambient for a period of around 5 to 120 seconds; and wherein the oxidizing ambient is comprised of: O
2
, O
3
, NO, N
2
O, H
2
O, and any combination thereof.


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Katoh, H., Yoshida

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